Invention Application
- Patent Title: DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
- Patent Title (中): CMOS混合方向的双路隔离
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Application No.: US13349203Application Date: 2012-01-12
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Publication No.: US20120104511A1Publication Date: 2012-05-03
- Inventor: Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- Applicant: Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Main IPC: H01L27/092
- IPC: H01L27/092
Abstract:
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
Public/Granted literature
- US09355887B2 Dual trench isolation for CMOS with hybrid orientations Public/Granted day:2016-05-31
Information query
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