A circuit that transfers data between a first clock domain using a first clock and a second clock domain using a second clock synchronized with the first clock. The circuit comprises a data holding circuit operating at the first clock, an enable signal generation circuit connected to the data holding circuit. Preferably, the data transfer circuit includes an edge signal generation circuit connected to the data holding circuit, the edge signal generation circuit generating an edge signal allowing the data holding circuit to receive and send the data when edges of the first clock and the second clock align, and applying the edge signal to the data holding circuit.