发明申请
US20120110367A1 Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses
有权
用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法
- 专利标题: Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses
- 专利标题(中): 用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法
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申请号: US12916661申请日: 2010-11-01
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公开(公告)号: US20120110367A1公开(公告)日: 2012-05-03
- 发明人: Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
- 申请人: Jentsung Ken Lin , Ajay Anant Ingle , Eai-hsin A. Kuo , Paul Douglas Bassett
- 申请人地址: US CA San Diego
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: US CA San Diego
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F9/34 ; G06F12/00 ; G06F12/08 ; G06F9/44
摘要:
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.