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1.发明授权Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses 有权用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法公开(公告)号：US08527804B2
公开(公告)日：2013-09-03
申请号：US12916661
申请日：2010-11-01
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3857
摘要： A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.
摘要翻译： 一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。 当至少一个指令不能在架构上完成时，延迟两个指令。 当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。 评估延迟足以评估两种指令是否可以在架构上完成。 评估延迟可以输入到写入控制，而不是存储器的读取控制。 可以调整存储器的预充电时钟以考虑评估延迟。 评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。
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2.发明申请Architecture and Method for Eliminating Store Buffers in a DSP/Processor with Multiple Memory Accesses 有权用于消除具有多个存储器访问的DSP /处理器中的存储缓冲器的架构和方法公开(公告)号：US20120110367A1
公开(公告)日：2012-05-03
申请号：US12916661
申请日：2010-11-01
CPC分类号： G06F9/3853 , G06F9/30043 , G06F9/3857
摘要： A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When at least one instruction cannot architecturally complete, delaying both instructions. When both instructions can architecturally complete and at least one is a write instruction, adjusting a write control of the memory to account for an evaluation delay. The evaluation delay can be sufficient to evaluate whether both instructions can architecturally complete. The evaluation delay can be input to the write control and not the read control of the memory. A precharge clock of the memory can be adjusted to account for the evaluation delay. Evaluating whether both instructions can architecturally complete can include determining whether data for each instruction is located in a cache, and whether the instructions are memory access instructions.
摘要翻译： 一种用于控制对存储器的系统访问的方法和装置，包括接收第一和第二指令，以及评估两种指令是否可以在架构上完成。 当至少一个指令不能在架构上完成时，延迟两个指令。 当两个指令都可以在架构上完成并且至少一个是写指令时，调整存储器的写入控制以考虑评估延迟。 评估延迟足以评估两种指令是否可以在架构上完成。 评估延迟可以输入到写入控制，而不是存储器的读取控制。 可以调整存储器的预充电时钟以考虑评估延迟。 评估两种指令是否可以在架构上完成可以包括确定每个指令的数据是否位于高速缓存中，以及指令是否是存储器访问指令。
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