If the frequency of a clock signal is increased, the pulse width of a sampling pulse is decreased, and the amount of time for a video signal to be written to a source line is inadequate. Sampling pulses (sam) rise sequentially in synchronization with the rise of a start pulse (SP). As the start pulse (SP) rises, synchronized with the rise of clock signals (CK, CKB), the sampling pulses (sam) fall off sequentially, delayed by half the period of the clock signals (CK, CKB) for every step. As a result, the sampling pulses (sam) with a pulse width longer than one period of the clock signals (CK, CKB) are generated. In a period Ta, a desired video signal (VIDEO) is written to its corresponding source line. In this way, the time for half a period of the clock signal can be secured for writing to the source line.