A semiconductor memory device includes a memory cell array, a tag information register, a refresh control circuit and a DQ pin. The memory cell array includes multiple memory cells divided into first cells and second cells according to corresponding data retention times. The tag information register stores refresh cycle information for each wordline connected to the first cells and the second cells. The refresh control circuit is configured to generate a refresh enable signal and a refresh address based on the refresh cycle information. The DQ pin is configured to output the refresh enable signal, the refresh address and data stored in the memory cell array.