A vertical semiconductor device includes a first pillar and a second pillar, a first bit line contact formed at a lower portion of a first sidewall of the first pillar, a second bit line contact formed at a lower portion of a second sidewall of the second pillar which face the first sidewall of the first pillar, a bit line commonly connected to the first bit line contact and the second bit line contact, and a gate formed at both sides of the first pillar and the second pillar to be crossed with the bit line.