公开(公告)号：US20120001255A1

公开(公告)日：2012-01-05

申请号：US12957100

申请日：2010-11-30

Applicant: Jin Won PARK

Inventor： Jin Won PARK

IPC: H01L29/78 ,  H01L21/302

CPC classification number: H01L27/10876 ,  H01L29/66666

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, particularly, to a semiconductor device including a vertical type gate and a method of forming the same. According to the present invention, a semiconductor device includes a vertical pillar which is protruded from a semiconductor substrate, has a vertical channel, and has a first width; an insulating layer which has a second width smaller than the first width, provided in both sides of the vertical pillar which is adjacent in a first direction; and a nitride film provided in a side wall of the insulating layer.

Abstract translation: 半导体器件及其制造方法技术领域本发明涉及一种半导体器件及其制造方法，特别涉及包括垂直型栅极的半导体器件及其形成方法。 根据本发明，半导体器件包括从半导体衬底突出的垂直柱，具有垂直沟道，并具有第一宽度; 绝缘层，其具有比所述第一宽度小的第二宽度，设置在所述垂直柱的在第一方向上相邻的两侧; 以及设置在绝缘层的侧壁中的氮化物膜。

公开(公告)号：US20110108946A1

公开(公告)日：2011-05-12

申请号：US12823999

申请日：2010-06-25

Applicant: Jin Won PARK

Inventor： Jin Won PARK

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fuse of a semiconductor device includes a fuse pattern separated by a blowing region formed on an interlayer insulating film, and a recess formed by removing a portion of the upper portion of a plurality of contacts disposed in the lower portion of the blowing region. After the fuse pattern is blown, the fuse pattern moves in the reliable environment, thereby preventing the electric short to improve yield of the semiconductor device.

Abstract translation: 半导体器件的熔丝包括由形成在层间绝缘膜上的吹制区域分离的熔丝图形，以及通过去除设置在吹风区域的下部的多个触点的上部的一部分而形成的凹部。 在熔丝图案熔断后，熔丝图案在可靠的环境中移动，从而防止电短路以提高半导体器件的产量。

公开(公告)号：US20120146136A1

公开(公告)日：2012-06-14

申请号：US13021143

申请日：2011-02-04

Applicant: Jin Won PARK

Inventor： Jin Won PARK

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10885 ,  H01L27/10876

Abstract: A vertical semiconductor device includes a first pillar and a second pillar, a first bit line contact formed at a lower portion of a first sidewall of the first pillar, a second bit line contact formed at a lower portion of a second sidewall of the second pillar which face the first sidewall of the first pillar, a bit line commonly connected to the first bit line contact and the second bit line contact, and a gate formed at both sides of the first pillar and the second pillar to be crossed with the bit line.

Abstract translation: 垂直半导体器件包括第一柱和第二柱，形成在第一柱的第一侧壁的下部的第一位线接触，形成在第二柱的第二侧壁的下部的第二位线接触 其面对第一柱的第一侧壁，通常连接到第一位线接触和第二位线接触的位线，以及形成在第一柱和第二柱的两侧以与位线交叉的栅极 。

公开(公告)号：US20110116084A1

公开(公告)日：2011-05-19

申请号：US12717688

申请日：2010-03-04

Applicant: Seung Seoup LEE ,  Tak Gyum KIM ,  Jin Won PARK

Inventor： Seung Seoup LEE ,  Tak Gyum KIM ,  Jin Won PARK

IPC: G01R31/308 ,  G01N21/956

CPC classification number: G01N21/95684 ,  G01R31/309

Abstract: Disclosed herein is a method of inspecting defects in a circuit pattern of a substrate. At least one laser beam radiation unit for radiating a laser beam onto an inspection target circuit pattern of a substrate in a non-contact manner is prepared. A probe beam radiation unit for radiating a probe beam onto a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner is prepared. The laser beam is radiated onto the inspection target circuit pattern using the laser beam radiation unit. The probe beam is radiated onto the connection circuit pattern using the probe beam radiation unit, thus measuring information about whether the probe beam is diffracted, and a diffraction angle. Accordingly, the method can solve problems such as erroneous measurements caused by contact pressure and can reduce the time required for measurements.

Abstract translation: 本文公开了一种检查基板的电路图案中的缺陷的方法。 制备用于以非接触方式将激光束照射到基板的检查对象电路图案上的至少一个激光束辐射单元。 准备用于以不接触的方式将探测光束照射到连接电路图案以电连接到检查对象电路图案的探测光束辐射单元。 使用激光束辐射单元将激光束照射到检查对象电路图案上。 使用探测光束辐射单元将探测光束照射到连接电路图案上，从而测量关于探针光束是否衍射的信息和衍射角。 因此，该方法可以解决诸如由接触压力引起的误差测量等问题，并且可以减少测量所需的时间。