发明申请
US20120151423A1 LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING 审中-公开
通过结构预处理的大规模形式分析

LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING
摘要:
An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.
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