公开(公告)号：US20120151423A1

公开(公告)日：2012-06-14

申请号：US13284489

申请日：2011-10-28

申请人： Jason R. Baumgartner ,  Tilman Gloekler ,  Christoph Jaeschke ,  Ralf Ludewig

发明人： Jason R. Baumgartner ,  Tilman Gloekler ,  Christoph Jaeschke ,  Ralf Ludewig

IPC分类号： G06F17/50

CPC分类号： G06F17/504

摘要： An improved method for performing a formal verification of a property in an electronic circuit design comprises: specifying at least one safety property in the electronic circuit design at a register-transfer level, setting boundaries of a logic cone to a start level according to a configurable structural design criterion, extracting the logic cone from the electronic circuit design based on the at least one specified safety property and the set boundaries, executing a formal verification tool on the logic cone to verify the at least one specified property, extending the boundary of the logic cone according to a configurable structural design criterion and performing the extracting and executing on the new logic cone, if the verification result does not satisfy the at least one safety property.

摘要翻译： 一种用于执行电子电路设计中的属性的形式验证的改进方法包括：在寄存器传送级别指定电子电路设计中的至少一个安全属性，根据可配置的方式将逻辑锥的边界设置为起始级别 结构设计标准，基于至少一个指定的安全属性和设定的边界，从电子电路设计中提取逻辑锥，在逻辑锥上执行形式验证工具，以验证至少一个指定的属性， 根据可配置结构设计标准的逻辑锥，并且如果验证结果不满足至少一个安全属性，则执行在新的逻辑锥上的提取和执行。

公开(公告)号：US08055931B2

公开(公告)日：2011-11-08

申请号：US12246123

申请日：2008-10-06

申请人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

发明人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

IPC分类号： G06F1/04

CPC分类号： G06F1/12

摘要： A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

摘要翻译： 提供了一种用于在对准元件内的两个振荡器信号之间切换的方法。 根据该方法，选择两个振荡器信号之一作为第一主信号，以便在对准元件的输出处提供输出步进信号。 该方法包括当两个振荡器信号之间的开关发生时或当检测到第一主信号的故障时引入虚拟步进信号。 该方法还包括在开关的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成。

公开(公告)号：US20090100283A1

公开(公告)日：2009-04-16

申请号：US12246123

申请日：2008-10-06

申请人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

发明人： Ralf Ludewig ,  Thuyen Le ,  Tilman Gloekler ,  Willm Hinrichs

IPC分类号： G06F1/12

CPC分类号： G06F1/12

摘要： A method for switching between two oscillator signals within an alignment element, wherein one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. Said method comprises the steps of: introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected; sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed; sending the virtual stepping signal to the output of the alignment element in the event of a failure in the master signal until a switch to the other oscillator signal as a new master signal is performed or until the first master signal becomes valid again.

摘要翻译： 一种用于在对准元件内切换两个振荡器信号的方法，其中两个振荡器信号之一被选择为第一主信号，以便在对准元件的输出处提供输出步进信号。 所述方法包括以下步骤：当发生两个振荡器信号之间的切换时或当检测到第一主信号的故障时，引入虚拟步进信号; 在切换的情况下将虚拟步进信号发送到对准元件的输出，直到与新的主信号的对准完成; 在主信号发生故障的情况下将虚拟步进信号发送到对准元件的输出，直到作为新的主信号切换到另一个振荡器信号，或者直到第一主信号再次变为有效。

公开(公告)号：US20090259899A1

公开(公告)日：2009-10-15

申请号：US12101208

申请日：2008-04-11

申请人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

发明人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

IPC分类号： G01R31/28

CPC分类号： G06F11/0784 ,  G06F11/0706 ,  G06F11/0778 ,  G06F11/2236

摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

摘要翻译： 在处理器中系统检查停止时自动扫描完成的方法。 处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。 该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里 如果没有发生系统检查停止，则已存储。

公开(公告)号：US08868960B2

公开(公告)日：2014-10-21

申请号：US13170466

申请日：2011-06-28

申请人： Tobias Bergmann ,  Ralf Ludewig ,  Tobias Webel ,  Ulrich Weiss

发明人： Tobias Bergmann ,  Ralf Ludewig ,  Tobias Webel ,  Ulrich Weiss

IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F15/16 ,  G06F1/32

CPC分类号： G06F1/12 ,  G06F1/3237 ,  Y02D10/128

摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

摘要翻译： 提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。 在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。 事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中，偏移计数器由参考时钟同步。

公开(公告)号：US08479070B2

公开(公告)日：2013-07-02

申请号：US12822287

申请日：2010-06-24

申请人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

发明人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

IPC分类号： G01R31/28

CPC分类号： G01R31/31701 ,  G01R31/3172

摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

摘要翻译： 集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器 功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

公开(公告)号：US20110320898A1

公开(公告)日：2011-12-29

申请号：US12822287

申请日：2010-06-24

申请人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

发明人： Ulrich Baur ,  Lawrence D. Curley ,  Ronald J. Frishmuth ,  Ralf Ludewig ,  Ching L. Tong ,  Tobias Webel

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31701 ,  G01R31/3172

摘要： An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

摘要翻译： 集成电路芯片包括通信地连接到第一输入/输出（I / O）引脚的主线功能逻辑路径，通信地连接到第一I / O引脚的测试逻辑路径，设置在测试逻辑之间的通信连接之间的锁存器 功能路径和第一I / O引脚，第二I / O引脚通信地连接到锁存器，第二I / O引脚可操作以发送操作以改变锁存器的状态的信号。

公开(公告)号：US20080276022A1

公开(公告)日：2008-11-06

申请号：US12110609

申请日：2008-04-28

申请人： Thuyen Le ,  Ralf Ludewig

发明人： Thuyen Le ,  Ralf Ludewig

IPC分类号： G06F13/36

CPC分类号： G06F13/4031

摘要： A method to resolve a deadlock in a bus architecture comprising a first and a second single-envelope bus with at least one master and one slave each, where the first and second single-envelope buses are arranged on different sides of an asynchronous boundary and are coupled via a bus bridge, said method comprising the steps of: granting the bus to a first master arranged on a first side of the asynchronous boundary which requests a transaction within a critical time window; monitoring the bus which has been granted for transaction to the first master; stealing silently the bus from the first master if a deadlock condition arises; granting the bus to a second master arranged on a second side of the asynchronous boundary raising the deadlock condition by requesting a second transaction within the critical time window; completing the second transaction to resolve the deadlock scenario; and returning back the bus to the first master to complete the first transaction. Further, a bus architecture to perform said method, a single-envelope bus architecture and a computer system comprising such a bus architecture are described.

摘要翻译： 一种用于解决总线架构中的死锁的方法，包括具有至少一个主机和一个从机的第一和第二单包线总线，其中第一和第二单包线总线布置在异步边界的不同侧上，并且是 所述方法包括以下步骤：将所述总线授予布置在异步边界第一侧上的第一主机，所述第一主机在紧急时间窗口内请求交易; 监控已授予交易给第一主人的公共汽车; 如果出现死锁状况，从第一位主人静静地偷走公共汽车; 将总线授予布置在异步边界的第二侧上的第二主机，通过在关键时间窗口内请求第二个事务来提高死锁状态; 完成第二次交易以解决死锁情景; 并将总线返回第一个主站完成第一个交易。 此外，描述了执行所述方法的总线架构，单包络总线架构和包括这种总线架构的计算机系统。

公开(公告)号：US07966536B2

公开(公告)日：2011-06-21

申请号：US12101208

申请日：2008-04-11

申请人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

发明人： Ralf Ludewig ,  Walter Niklaus ,  Dietmar Schmunkamp ,  Scott Barnett Swaney ,  Tobias Webel

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/0784 ,  G06F11/0706 ,  G06F11/0778 ,  G06F11/2236

摘要： A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

摘要翻译： 在处理器中系统检查停止时自动扫描完成的方法。 处理器包括：处理器寄存器; 连接在处理器寄存器和检查站扫描控制器之间的millicode接口; 连接在止回扫描控制器和检查停止扫描引擎之间的止回逻辑电路; 以及连接到检查停止扫描引擎的扫描链引擎和扫描链。 该方法包括（a）在发生从处理器寄存器串行读取数据的检查站并将数据串行写入扫描链寄存器的锁存器时; 和（b）在（a）期间发生系统检查停止时，停止在系统检查停止期间发送的读取和写入数据，并且在发生系统检查停止时存储数据的扫描链的锁存器中移动数据，以锁定数据将在哪里 如果没有发生系统检查停止，则已存储。

公开(公告)号：US07788432B2

公开(公告)日：2010-08-31

申请号：US12244430

申请日：2008-10-02

申请人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

发明人： Ralf Ludewig ,  Thuyen Le ,  Tobias Webel ,  Klaus Peter Gungl

IPC分类号： G06F13/00

CPC分类号： G06F13/4286

摘要： The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.

摘要翻译： 这里描述的各种实施例涉及用于在中央控制块和半导体芯片内的多个卫星部件之间执行串行通信的系统。 该系统包括将卫星组件串行连接到中央控制块的至少一个逻辑环。 该系统还包括集中式定时器。 卫星组件帮助系统服从协议并执行对寄存器的访问和/或从寄存器的直接访问。 逻辑环包括提供用于发送数据分组和地址分组的至少一个数据信道。 实施单包络交易。 与单包络事务相关联的卫星组件的错误作为附加确认信息报告给中央控制块。