发明申请
- 专利标题： SPUR REDUCTION TECHNIQUE FOR SAMPLING PLL'S
- 专利标题（中）： 用于采样PLL的减少技术
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申请号： US12973353申请日： 2010-12-20
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公开(公告)号： US20120154003A1公开(公告)日： 2012-06-21
- 发明人: Xiang Gao , Ahmad Bahai , Mounir Bohsali , Ali Djabbari , Eric Klumperink , Bram Nauta , Gerard Socci
- 申请人： Xiang Gao , Ahmad Bahai , Mounir Bohsali , Ali Djabbari , Eric Klumperink , Bram Nauta , Gerard Socci
- 申请人地址： US CA Santa Clara
- 专利权人： National Semiconductor Corporation
- 当前专利权人： National Semiconductor Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H03L7/091
- IPC分类号： H03L7/091
摘要：
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced.
公开/授权文献
- US08373481B2 Spur reduction technique for sampling PLL's 公开/授权日：2013-02-12
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