发明申请
US20120156865A1 Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping
有权
通过晚期栅极掺杂增强半导体器件的栅极电极的图案化均匀性
- 专利标题： Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping
- 专利标题（中）： 通过晚期栅极掺杂增强半导体器件的栅极电极的图案化均匀性
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申请号： US13189997申请日： 2011-07-25
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公开(公告)号： US20120156865A1公开(公告)日： 2012-06-21
- 发明人: Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
- 申请人： Hans-Juergen Thees , Sven Beyer , Martin Mazur , Steffen Laufer
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人： GLOBALFOUNDRIES INC.
- 当前专利权人地址： KY Grand Cayman
- 优先权： DE102010063778.5 20101221
- 主分类号： H01L21/28
- IPC分类号： H01L21/28
摘要：
When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.
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