发明申请
- 专利标题: Constructing a Clock Tree for an Integrated Circuit Design
- 专利标题(中): 构建集成电路设计的时钟树
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申请号: US13325102申请日: 2011-12-14
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公开(公告)号: US20120159416A1公开(公告)日: 2012-06-21
- 发明人: Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
- 申请人: Guofan Jiang , Yi Fan Lin , Yang Liu , Hao Yang
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 优先权: CN201010612330.8 20101220
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.
公开/授权文献
- US08484604B2 Constructing a clock tree for an integrated circuit design 公开/授权日:2013-07-09