公开(公告)号：US20120159416A1

公开(公告)日：2012-06-21

申请号：US13325102

申请日：2011-12-14

申请人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

发明人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/62

摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

摘要翻译： 公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小， 其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。

公开(公告)号：US08484604B2

公开(公告)日：2013-07-09

申请号：US13325102

申请日：2011-12-14

申请人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

发明人： Guofan Jiang ,  Yi Fan Lin ,  Yang Liu ,  Hao Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/62

摘要： A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices.

摘要翻译： 公开了一种用于构建用于集成电路设计的时钟树的方法和装置，所述方法包括：通过对放置的网表执行定时分析来提取放置的网表中的顺序设备之间的路径延迟; 以及根据所述顺序设备之间的路径延迟构建用于驱动所述顺序设备的时钟树，以使得任何两个顺序设备之间的定时延迟的乘积和所述两个顺序设备的时钟树分支权重之和最小， 其中两个顺序设备的时钟树分支权重与从时钟树分支点相对于两个顺序设备到两个顺序设备的时钟树电平的数量正相关。