发明申请
- 专利标题: REFERENCE VOLTAGE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
- 专利标题(中): 参考电压电路和半导体集成电路
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申请号: US13316522申请日: 2011-12-11
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公开(公告)号: US20120212194A1公开(公告)日: 2012-08-23
- 发明人: Suguru TACHIBANA , Hiroyuki Matsunami , Yukinobu Tanida
- 申请人: Suguru TACHIBANA , Hiroyuki Matsunami , Yukinobu Tanida
- 申请人地址: JP Yokohama-shi
- 专利权人: FUJITSU SEMICONDUCTOR LIMITED
- 当前专利权人: FUJITSU SEMICONDUCTOR LIMITED
- 当前专利权人地址: JP Yokohama-shi
- 优先权: JP2011-036712 20110223
- 主分类号: G05F1/10
- IPC分类号: G05F1/10
摘要:
A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.