公开(公告)号：US08508307B2

公开(公告)日：2013-08-13

申请号：US13158054

申请日：2011-06-10

申请人： Kazuhiro Mitsuda ,  Koji Okada ,  Suguru Tachibana

发明人： Kazuhiro Mitsuda ,  Koji Okada ,  Suguru Tachibana

IPC分类号： H03L1/02 ,  H03K3/26 ,  H03K3/353

CPC分类号： H03L1/04 ,  G05F3/30 ,  H03K3/011 ,  H03K3/027

摘要： An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.

摘要翻译： 一种包括参考电压产生电路的振荡电路，其将与绝对温度成比例增加的比例绝对温度（PTAT）输出添加到互补绝对温度（CTAT）输出，其降低 与绝对温度成比例，以产生和输出参考电压。 振荡电路产生具有期望和固定频率的振荡信号。

公开(公告)号：US08436687B2

公开(公告)日：2013-05-07

申请号：US12974996

申请日：2010-12-21

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H03K3/03

CPC分类号： H03K3/354

摘要： An oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node.

摘要翻译： 振荡装置包括：传输门，包括P沟道晶体管和N沟道晶体管; 第一反相器，用于反转传输门的输出信号并输出​​转移门的反相输出信号; 第二逆变器，用于反相第一反相器的输出信号，并输出第一反相器的反相输出信号; 第三反相器，用于反相第一反相器的输出信号并输出​​第一反相器的反相输出信号; 第四反相器，用于反相第三反相器的输出信号，并将第三反相器的反相输出信号输出到传输门的输入端; 连接在所述传输门的输出端和所述第二反相器的输出端之间的第一电容器; 以及连接在传输门的输出端和参考电位节点之间的第二电容器。

公开(公告)号：US20120075128A1

公开(公告)日：2012-03-29

申请号：US13186059

申请日：2011-07-19

申请人： Kenta ARUGA ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

发明人： Kenta ARUGA ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

IPC分类号： H03M1/12

CPC分类号： H03M1/1038 ,  H03M1/1019 ,  H03M1/144 ,  H03M1/468 ,  H03M1/765 ,  H03M1/804

摘要： A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

摘要翻译： 逐次逼近A / D转换器，具有耦合到顶部节点和开关组的电容元件组的主DAC; 比较上位节点电压和比较参考电压的比较器; 校正DAC根据要在主DAC中平衡的电容元件对的电容误差产生校正电压，并向顶部节点提供校正电压; 以及控制电路，产生用于控制开关组的内部数字输入和用于控制校正电压的校正码，并且当执行A / D转换时，通过比较器输出逐次逼近结果。 控制电路测量要平衡的电容元件对的电容误差，并确定偏移消除的电容误差，其中在测量中产生的偏移从电容误差中消除。

公开(公告)号：US07948304B2

公开(公告)日：2011-05-24

申请号：US12619496

申请日：2009-11-16

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A constant-voltage generating circuit includes: a reference potential generating unit; first and second amplifier units whose outputs are respectively connected to the output line; and a low-pass filter, and wherein first and second operation periods are repeated, one alternating with the other, the first amplifier unit stores offset voltage of the first amplifier unit during the second operation period, and produces an output, during the first operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage, and the second amplifier unit stores offset voltage of the second amplifier unit during the first operation period, and produces an output, during the second operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage.

摘要翻译： 恒压发生电路包括：基准电位发生单元; 第一和第二放大器单元，其输出分别连接到输出线; 和低通滤波器，并且其中重复第一和第二操作周期，一个与另一个交替，第一放大器单元在第二操作周期期间存储第一放大器单元的偏移电压，并且在第一操作期间产生输出 周期，其通过使用所存储的偏移电压消除偏移电压使第一电位和第二电位彼此相等，并且第二放大器单元在第一操作周期期间存储第二放大器单元的偏移电压，并且产生输出 在第二操作期间，通过使用存储的偏移电压消除偏移电压，使第一电位和第二电位彼此相等。

公开(公告)号：US20070252573A1

公开(公告)日：2007-11-01

申请号：US11589139

申请日：2006-10-30

申请人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kenta Aruga ,  Tatsuo Kato

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A reference voltage generation circuit has transistors generating a PTAT current that increases in proportion to temperature, a transistor generating a CTAT current that decreases in proportion to temperature, a first variable resistor adjusting an output voltage, a transistor supplying the PTAT current to the first variable resistor via a first switch, a transistor supplying the CTAT current to the first variable resistor via a second switch, and a second variable resistor adjusting the CTAT current. The first switch is on in first and third operation modes and off in a second operation mode. The second switch is on in the first and second operation modes and off in the third operation mode. Switching the operation modes realizes independently outputting a PTAT voltage or a CTAT voltage. Independently adjusting the voltages makes it possible to correct output reference voltage of the reference voltage generation circuit accurately at low cost.

摘要翻译： 参考电压产生电路具有产生与温度成比例地增加的PTAT电流的晶体管，产生与温度成比例地降低的CTAT电流的晶体管，调节输出电压的第一可变电阻器，将PTAT电流提供给第一变量的晶体管 经由第一开关的电阻器，经由第二开关将CTAT电流提供给第一可变电阻器的晶体管，以及调节CTAT电流的第二可变电阻器。 在第一和第三操作模式下，第一开关处于开启状态，并在第二操作模式中关闭。 第二开关在第一和第二操作模式中接通，并且在第三操作模式中断开。 切换操作模式可实现独立输出PTAT电压或CTAT电压。 独立地调节电压可以以低成本准确地校正参考电压产生电路的输出参考电压。

公开(公告)号：US07233273B2

公开(公告)日：2007-06-19

申请号：US11363968

申请日：2006-03-01

申请人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

IPC分类号： H03M1/12

CPC分类号： H03M1/1023 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/804

摘要： Included are a first unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the first analog signal, a second unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the second analog signal, a first switch connecting the first unit to an output side of the second unit, a comparator comparing a differential value between the first analog signal and the second analog signal with a differential value between the comparison signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of the first analog terminal and the second analog terminal.

摘要翻译： 包括第一单元，包括DAC，其产生用作与第一模拟信号进行比较的对象的比较信号，接收并保持第一模拟信号;第二单元，包括DAC，其产生用作对象的比较信号 与所述第一模拟信号进行比较，接收和保持所述第二模拟信号，将所述第一单元连接到所述第二单元的输出侧的第一开关，将所述第一模拟信号和所述第二模拟信号之间的差分值与 第一DAC的比较信号和第二DAC的输出信号之间的差分值以及控制第一模拟端子和第二模拟端子的电位波动的电位控制电路。

公开(公告)号：US20070115041A1

公开(公告)日：2007-05-24

申请号：US11650485

申请日：2007-01-08

申请人： Suguru Tachibana ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Tatsuo Kato

IPC分类号： H03L5/00

CPC分类号： H03K3/356113 ,  H03K17/102 ,  H03K17/223

摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

公开(公告)号：US07199745B2

公开(公告)日：2007-04-03

申请号：US11273025

申请日：2005-11-15

申请人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

发明人： Suguru Tachibana ,  Kazuhiro Mitsuda ,  Tatsuo Kato

IPC分类号： H03M1/34

CPC分类号： H03M1/468 ,  H03M1/0682

摘要： A successive approximation A/D converter includes a sample-hold amplifier circuit configured to sample and hold an input analog voltage to produce an internal analog voltage proportional to the input analog voltage with a voltage gain being smaller than 1, a switched capacitor D/A converter coupled to the sample-hold amplifier circuit and including a plurality of capacitors for storing electric charge responsive to the internal analog voltage, the switched capacitor D/A converter configured to switch couplings of the capacitors in response to a control signal to produce a comparison analog voltage responsive to the internal analog voltage and the control signal, a comparator coupled to the switched capacitor D/A converter to produce a comparison result signal responsive to the comparison analog voltage, and a control circuit coupled to the comparator to supply the control signal responsive to the comparison result signal to the switched capacitor D/A converter.

摘要翻译： 逐次逼近A / D转换器包括采样保持放大器电路，其被配置为采样和保持输入模拟电压以产生与输入模拟电压成比例的内部模拟电压，其电压增益小于1，开关电容器D / A 转换器，其耦合到采样保持放大器电路，并且包括用于响应于内部模拟电压存储电荷的多个电容器，所述开关电容器D / A转换器被配置为响应于控制信号来切换电容器的耦合以产生比较 响应于内部模拟电压和控制信号的模拟电压，耦合到开关电容器D / A转换器的比较器，以响应于比较模拟电压产生比较结果信号;以及控制电路，耦合到比较器以提供控制信号 响应于比较结果信号到开关电容器D / A转换器。

公开(公告)号：US20050280084A1

公开(公告)日：2005-12-22

申请号：US10965856

申请日：2004-10-18

申请人： Tomonari Morishita ,  Hideo Nunokawa ,  Suguru Tachibana ,  Fukuji Kihara

发明人： Tomonari Morishita ,  Hideo Nunokawa ,  Suguru Tachibana ,  Fukuji Kihara

IPC分类号： H01L27/08 ,  H01L29/76

CPC分类号： H01L27/0811

摘要： A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.

摘要翻译： 可以防止MOS电容器中的栅极氧化物的电介质击穿并且可以减小电路面积的半导体器件。 半导体器件包括NMOS晶体管，栅极连接到高电位侧的端子VDD和PMOS晶体管，其栅极连接到低电位侧的端子GND，源极/漏极（S / D） NMOS晶体管的区域和PMOS晶体管的源极/漏极（S / D）区域电连接。

公开(公告)号：US06353569B1

公开(公告)日：2002-03-05

申请号：US09291272

申请日：1999-04-14

申请人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

发明人： Hiroyuki Mizuno ,  Suguru Tachibana ,  Koichiro Ishibashi ,  Kenichi Osada

IPC分类号： G11C1300

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C5/063 ,  G11C7/06 ,  G11C7/22 ,  G11C2207/108 ,  Y02D10/13

摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

摘要翻译： 存储器结构/电路具有至少两个相互连接的存储单元阵列。 两个或多个存储单元阵列的位线通过分层开关连接。 通过使用层次结构开关选择一个阵列而不选择其他阵列，其中一个阵列的存储单元可以比其他阵列更快地读出。 因此，如果存储在更快的访问存储器阵列中，则可以更快地选择性地读出更高频率读取的数据。 如果快速访问存储单元阵列中的数据包含另一阵列中的数据副本，则可以将其用作高速缓冲存储器。 组合的标签阵列和数据阵列通过分层交换机连接组合连接到另一标签阵列和数据阵列，可以提供直接映射或设置关联的高速缓存存储器，也可以是完全关联的。 存储器件可用于具有CPU的半导体数据处理器，其中存储器件通过总线连接到CPU，其中CPU和存储器件均形成在单个半导体衬底上。 存储器件也可以是片外器件。