In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.