发明申请
US20120248501A1 SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE
有权
自对准III-V场效应晶体管（FET），具有自对准III-V FET的集成电路（IC）芯片及其制造方法
- 专利标题： SELF-ALIGNED III-V FIELD EFFECT TRANSISTOR (FET), INTEGRATED CIRCUIT (IC) CHIP WITH SELF-ALIGNED III-V FETS AND METHOD OF MANUFACTURE
- 专利标题（中）： 自对准III-V场效应晶体管（FET），具有自对准III-V FET的集成电路（IC）芯片及其制造方法
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申请号： US13074854申请日： 2011-03-29
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公开(公告)号： US20120248501A1公开(公告)日： 2012-10-04
- 发明人: Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
- 申请人： Cheng-Wei Cheng , Shu-Jen Han , Kuen-Ting Shiu
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L21/336
摘要：
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.
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