公开(公告)号：US09079269B2

公开(公告)日：2015-07-14

申请号：US13302427

申请日：2011-11-22

Applicant: Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Norma E. Sosa Cortes ,  Ning Li ,  Ibrahim Alhomoudi

IPC: B23K26/00 ,  H01L21/304 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/268 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/6835 ,  H01L2221/68327

Abstract: Laser ablation can be used to form a trench within at least a blanket layer of a stressor layer that is atop a base substrate. A non-ablated portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can also be used to form a trench within a blanket material stack including at least a plating seed layer. A stressor layer is formed on the non-ablated portions of the material stack and one portion of the stressor layer has an edge that defines the edge of the material layer region to be spalled. Laser ablation can be further used to form a trench that extends through a blanket stressor layer and into the base substrate itself. The trench has an edge that defines the edge of the material layer region to be spalled.

Abstract translation: 可以使用激光烧蚀在至少基底衬底顶部的应力层的至少一层覆盖层内形成沟槽。 应力层的非烧蚀部分具有限定要剥离的材料层区域的边缘的边缘。 激光烧蚀还可用于在包括至少镀覆种子层的覆盖材料堆叠内形成沟槽。 在材料堆叠的非烧蚀部分上形成应力层，应力层的一部分具有限定要剥离的材料层区域的边缘的边缘。 可以进一步使用激光烧蚀来形成延伸穿过覆盖应力层并进入基底本身的沟槽。 沟槽具有限定要剥离的材料层区域的边缘的边缘。

公开(公告)号：US09040392B2

公开(公告)日：2015-05-26

申请号：US13161260

申请日：2011-06-15

Applicant: Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

IPC: H01L21/36 ,  H01L21/18 ,  H01L21/78 ,  H01L21/02 ,  H01L31/18

CPC classification number: H01L21/187 ,  H01L21/02002 ,  H01L21/7813 ,  H01L31/1892 ,  Y02E10/50

Abstract: A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

公开(公告)号：US08828824B2

公开(公告)日：2014-09-09

申请号：US13074878

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Ko-Tao Lee ,  Kuen-Ting Shiu

IPC: H01L21/336

CPC classification number: H01L29/7781 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/66462 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations define FET pedestals on a layered semiconductor wafer that may include a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). A dielectric material, e.g., Aluminum Oxide (AlO), surrounds pedestals at least in FET source/drain regions. A conductive cap caps channel sidewalls at opposite channel ends. III-V on insulator (IIIVOI) devices form wherever the dielectric material layer is thicker than half the device length. Source/drain contacts are formed to the caps and terminate in/above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置在可以包括III-V半导体表面层（例如砷化镓（GaAs））和掩埋层（例如AlAs）的分层半导体晶片上限定FET基座。 介电材料，例如氧化铝（AlO），至少在FET源极/漏极区域中围绕基座。 导电盖帽在相对的通道端部封闭通道侧壁。 绝缘体上的III-V（IIIVOI）器件形成电介质材料层的厚度超过器件长度的一半。 源极/漏极触点形成到盖并终止在掩埋层中的介电材料之中/之上。

公开(公告)号：US08604519B2

公开(公告)日：2013-12-10

申请号：US13487473

申请日：2012-06-04

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/66 ,  H01L21/02 ,  H01L31/06

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US08466493B2

公开(公告)日：2013-06-18

申请号：US13074854

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/4763

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US20130082356A1

公开(公告)日：2013-04-04

申请号：US13603927

申请日：2012-09-05

Applicant: Cheng-Wei Cheng ,  Ning Li ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Ning Li ,  Kuen-Ting Shiu

IPC: H01L29/20

CPC classification number: H01L29/20 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02507 ,  H01L21/30612 ,  H01L21/7813

Abstract: In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.

Abstract translation: 在一个实施例中，提供了一种半导体结构，其包括基底衬底和位于基底衬底上的多层叠层。 多层堆叠包括从底部到顶部具有第一厚度的第一牺牲材料层，第一半导体器件层，具有第二厚度的第二牺牲材料层和第二半导体器件层，其中第一厚度小于 第二厚度。

公开(公告)号：US20130071999A1

公开(公告)日：2013-03-21

申请号：US13236119

申请日：2011-09-19

Applicant: Cheng-Wei Cheng ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Kuen-Ting Shiu

IPC: H01L21/20

CPC classification number: H01L21/30604 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02461 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02664 ,  H01L21/30612 ,  H01L21/7813

Abstract: A method of removing a semiconductor device layer from an underlying base substrate is provided in which a sacrificial phosphide-containing layer is formed between a semiconductor device layer and a base substrate. In some embodiments, a semiconductor buffer layer can be formed on an upper surface of the base substrate prior to forming the sacrificial phosphide-buffer layer. The resultant structure is then etched utilizing a non-HF etchant to release the semiconductor device layer from the base semiconductor substrate. After releasing the semiconductor device layer from the base substrate, the base substrate can be re-used.

Abstract translation: 提供了从下面的基底基板去除半导体器件层的方法，其中在半导体器件层和基底衬底之间形成牺牲磷化物层。 在一些实施例中，半导体缓冲层可以在形成牺牲磷化物缓冲层之前形成在基底衬底的上表面上。 然后使用非HF蚀刻剂蚀刻所得到的结构，以从半导体衬底释放半导体器件层。 在从基底基板释放半导体器件层之后，可以重新使用基底衬底。

公开(公告)号：US20120248501A1

公开(公告)日：2012-10-04

申请号：US13074854

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US09818901B2

公开(公告)日：2017-11-14

申请号：US13107371

申请日：2011-05-13

Applicant: Stephen W. Bedell ,  Cheng-Wei Cheng ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Norma E. Sosa Cortes

IPC: H01L31/18 ,  H01L31/0687

CPC classification number: H01L31/0687 ,  H01L31/18 ,  Y02E10/544

Abstract: A photovoltaic device and method for fabrication include multijunction cells, each cell having a material grown independently from the other and including different band gap energies. An interface is disposed between the cells and configured to wafer bond the cells wherein the cells are configured to be adjacent without regard to lattice mismatch.

公开(公告)号：US20140007932A1

公开(公告)日：2014-01-09

申请号：US13568121

申请日：2012-08-06

Applicant: Stephen W. Bedell ,  Cheng-Wei Cheng ,  Bahman Hekmatshoartabari ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Bahman Hekmatshoartabari ,  Ning Li ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC: H01L31/074

CPC classification number: H01L31/06875 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02664 ,  H01L31/03042 ,  H01L31/0735 ,  H01L31/1844 ,  Y02E10/544 ,  Y02P70/521

Abstract: Solar cell structures include stacked layers in reverse order on a germanium substrate wherein a n++ (In)GaAs buffer layer plays dual roles as buffer and contact layers in the inverted structures. The absorbing layers employed in such exemplary structures are III-V layers such as (In)GaAs. Controlled spalling may be employed as part of the fabrication process for the solar cell structures, which may be single or multi-junction. The requirement for etching a buffer layer is eliminated, thereby facilitating the manufacturing process of devices using the disclosed structures.

Abstract translation: 太阳能电池结构在锗衬底上以相反的顺序包括堆叠层，其中n ++（In）GaAs缓冲层在倒置结构中起缓冲层和接触层的双重作用。 在这种示例性结构中采用的吸收层是III-V层，例如（In）GaAs。 受控的剥落可以用作太阳能电池结构的制造过程的一部分，其可以是单结或多结。 消除了蚀刻缓冲层的要求，从而便于使用公开的结构的器件的制造过程。