A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.