公开(公告)号：US20120229171A1

公开(公告)日：2012-09-13

申请号：US13412653

申请日：2012-03-06

申请人： Liming Xiu ,  Ming-Chieh Lin

发明人： Liming Xiu ,  Ming-Chieh Lin

IPC分类号： H03B21/00

CPC分类号： G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

摘要： One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

摘要翻译： 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

公开(公告)号：US20120187999A1

公开(公告)日：2012-07-26

申请号：US13044566

申请日：2011-03-10

申请人： Ming-Chieh Lin

发明人： Ming-Chieh Lin

IPC分类号： G06G7/12

CPC分类号： G06F7/544

摘要： An interpolation circuit adapted to receive a plurality of inputs is provided. The inputs include a first input group and a second input group. The interpolation circuit includes a first selecting channel, a second selecting channel, and an interpolation unit. The first selecting channel receives the first input group and outputs a first input of the first input group according to a selecting signal. The second selecting channel receives the second input group and the first input and outputs a second input of the second input group according to the selecting signal. The first selecting channel and the second selecting channel respectively output the first input or the second input. The interpolation unit is coupled to the first selecting channel and the second selecting channel, and receives the first input and the second input, and accordingly performs an interpolation to output an interpolation result.

摘要翻译： 提供了适于接收多个输入的内插电路。 输入包括第一输入组和第二输入组。 插值电路包括第一选择信道，第二选择信道和插值单元。 第一选择通道接收第一输入组，并根据选择信号输出第一输入组的第一输入。 第二选择通道接收第二输入组和第一输入，并根据选择信号输出第二输入组的第二输入。 第一选择通道和第二选择通道分别输出第一输入或第二输入。 插值单元耦合到第一选择通道和第二选择通道，并且接收第一输入和第二输入，并且因此执行插值以输出插值结果。

公开(公告)号：US07678659B2

公开(公告)日：2010-03-16

申请号：US11421771

申请日：2006-06-02

申请人： Chao-Chun Tu ,  Ming-Chieh Lin

发明人： Chao-Chun Tu ,  Ming-Chieh Lin

IPC分类号： H01L21/00

CPC分类号： H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

摘要翻译： 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。

公开(公告)号：US20070072361A1

公开(公告)日：2007-03-29

申请号：US11421771

申请日：2006-06-02

申请人： Chao-Chun Tu ,  Ming-Chieh Lin

发明人： Chao-Chun Tu ,  Ming-Chieh Lin

IPC分类号： H01L21/8242 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036

CPC分类号： H01L21/76816 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.

摘要翻译： 一种用于减小半导体电容器中的漏电流的方法。 该方法包括提供用于收集电荷的顶板，提供用于收集与顶板相反的电荷的底板，提供用于在顶板和底板之间绝缘的介电层，提供顶部接触，提供底部接触， 提供多个通孔，包括用于将顶板连接到顶部触点的顶部通孔，以及用于将底板连接到底部触点的底部通孔; 以及分离通孔和相邻结构，使得它们的距离大于制造半导体电容器的半导体工艺的铸造设计规则的最小经过间隔要求。

公开(公告)号：US20130114072A1

公开(公告)日：2013-05-09

申请号：US13288941

申请日：2011-11-03

申请人： TSUN-YI WANG ,  MING-CHIEH LIN

发明人： TSUN-YI WANG ,  MING-CHIEH LIN

IPC分类号： G01J1/42

CPC分类号： H02S50/00 ,  H02S50/10

摘要： A solar cell inspection method and apparatus are disclosed. An embodiment of the solar cell inspection method includes the steps of: charging a diffusion capacitance of a solar cell; after charging the diffusion capacitance, discharging the diffusion capacitance; and detecting light emitted by the solar cell during the discharging step.

摘要翻译： 公开了一种太阳能电池检查方法和装置。 太阳能电池检查方法的一个实施例包括以下步骤：对太阳能电池的扩散电容进行充电; 在对扩散电容进行充电之后，对扩散电容进行放电; 以及在放电步骤期间检测太阳能电池发出的光。

公开(公告)号：US20120287140A1

公开(公告)日：2012-11-15

申请号：US13420587

申请日：2012-03-14

申请人： Ming-Chieh Lin ,  Ying-Yu Kuo ,  Wei-Ying Tu

发明人： Ming-Chieh Lin ,  Ying-Yu Kuo ,  Wei-Ying Tu

IPC分类号： G09G3/36 ,  G06F13/14

CPC分类号： G09G3/2096 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2360/127 ,  G09G2370/10

摘要： A display interface circuit includes a physical layer circuit for receiving and modulating an original data signal and an original clock signal, a frame buffer for storing and outputting the data signal according to the clock signal and a command signal, a display serial interface for transmitting the data signal and the clock signal through packetization, a configuration register for generating the command signal according to an asynchronous clock signal and the data signal, and an asynchronous delay circuit for adjusting a clock latency that the clock signal takes to be sent to the configuration register to generate the asynchronous clock signal.

摘要翻译： 显示接口电路包括用于接收和调制原始数据信号和原始时钟信号的物理层电路，用于根据时钟信号和命令信号存储和输出数据信号的帧缓冲器，用于发送 数据信号和通过分组化的时钟信号，用于根据异步时钟信号和数据信号产生命令信号的配置寄存器，以及用于调整时钟信号需要发送到配置寄存器的时钟延迟的异步延迟电路 以产生异步时钟信号。

公开(公告)号：US20110096219A1

公开(公告)日：2011-04-28

申请号：US12795837

申请日：2010-06-08

申请人： Pen-Jung Lee ,  Yu-Te Hsieh ,  Chiung-Kun Chuang ,  Ling-Ta Su ,  Ming-Chieh Lin

发明人： Pen-Jung Lee ,  Yu-Te Hsieh ,  Chiung-Kun Chuang ,  Ling-Ta Su ,  Ming-Chieh Lin

IPC分类号： H04N5/335 ,  H01L31/18

CPC分类号： H01L31/0203 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L31/02325 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An image sensor package includes a substrate, an image sensor chip, a plurality of metal wires and an encapsulant. The substrate has an upper face, a lower face and a plurality of connecting pads arranged on the upper face. The image sensor chip has an active surface, a back surface opposite to the active surface and a plurality of bonding pads arranged on the active surface. The metal wires electrically connect the bonding pads of the image sensor chip to the connecting pads of the substrate. The transparent cover is arranged above the image sensor chip. A gap is formed between the transparent cover and the image sensor chip. The encapsulant is disposed around the transparent cover and the metal wires, and is used for sealing the metal wires and fixing the transparent cover above the image sensor chip.

摘要翻译： 图像传感器封装包括基板，图像传感器芯片，多个金属线和密封剂。 基板具有上表面，下表面和布置在上表面上的多个连接焊盘。 图像传感器芯片具有活性表面，与活性表面相对的后表面和布置在活性表面上的多个接合焊盘。 金属线将图像传感器芯片的接合焊盘电连接到衬底的连接焊盘。 透明盖布置在图像传感器芯片的上方。 在透明盖和图像传感器芯片之间形成间隙。 密封剂设置在透明盖和金属丝周围，用于密封金属线并将透明盖固定在图像传感器芯片上方。

公开(公告)号：US09432790B2

公开(公告)日：2016-08-30

申请号：US12573157

申请日：2009-10-05

申请人： Nikunj Raghuvanshi ,  John Michael Snyder ,  Ming Chieh Lin ,  Naga K. Govindaraju

发明人： Nikunj Raghuvanshi ,  John Michael Snyder ,  Ming Chieh Lin ,  Naga K. Govindaraju

IPC分类号： H04R5/00 ,  H04S7/00 ,  A63F13/54 ,  H04M3/56

CPC分类号： H04S7/30 ,  A63F13/54 ,  A63F2300/6081 ,  G10H2250/531 ,  H04M3/56 ,  H04S7/302 ,  H04S7/305 ,  H04S2400/11

摘要： Described herein are techniques pertaining to real-time propagation of an arbitrary audio signal in a fixed virtual environment with dynamic audio sources and receivers. A wave-based numerical simulator is configured to compute response signals in the virtual environment with respect to a sample signal at various source and receiver locations. The response signals are compressed and placed in the frequency domain to generate frequency responses. Such frequency responses are selectively convolved with the arbitrary audio signal to allow real-time propagation with moving sources and receivers in the virtual environment.

摘要翻译： 这里描述的是与具有动态音频源和接收器的固定虚拟环境中的任意音频信号的实时传播有关的技术。 基于波形的数值模拟器被配置为相对于在各种源和接收器位置处的采样信号计算虚拟环境中的响应信号。 响应信号被压缩并放置在频域中以产生频率响应。 这种频率响应与任意音频信号选择性卷积，以允许与虚拟环境中的移动源和接收器的实时传播。

公开(公告)号：US08321609B2

公开(公告)日：2012-11-27

申请号：US11612487

申请日：2006-12-19

申请人： Ming-Chieh Lin ,  Hsieh-Yi Wu

发明人： Ming-Chieh Lin ,  Hsieh-Yi Wu

IPC分类号： G06F3/00

CPC分类号： G06F1/3203

摘要： A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a clock signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the clock signal is turned off so that the power consumed by the clock signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.

摘要翻译： 提供一种适用于包括先进先出（FIFO）寄存器的电路的省电控制电路和方法。 在本发明中，逻辑电路设置在两个电路模块之间，其间传输数据。 当数据输入FIFO寄存器时，逻辑电路激活接收端的电路模块的时钟信号，以读取数据。 当读取存储在FIFO寄存器中的所有数据时，时钟信号被关闭，从而在不影响数据传输效率的情况下降低时钟信号消耗的功率，从而达到省电的目的。

公开(公告)号：US20080126713A1

公开(公告)日：2008-05-29

申请号：US11612487

申请日：2006-12-19

申请人： Ming-Chieh Lin ,  Hsieh-Yi Wu

发明人： Ming-Chieh Lin ,  Hsieh-Yi Wu

IPC分类号： G06F12/00

CPC分类号： G06F1/3203

摘要： A power-saving control circuit and method suitable for circuits including a first-in-first-out (FIFO) register is provided. In the present invention, a logic circuit is disposed between two circuit modules with data transmitted in between. When there is data input into the FIFO register, the logic circuit activates a pulse signal of the circuit module in the receiving end for reading the data. When all the data stored in the FIFO register is read, the pulse signal is turned off so that the power consumed by the pulse signal is reduced without affecting the data transmitting efficiency and the purpose of power-saving is achieved.

摘要翻译： 提供一种适用于包括先进先出（FIFO）寄存器的电路的省电控制电路和方法。 在本发明中，逻辑电路设置在两个电路模块之间，其间传输数据。 当数据输入到FIFO寄存器中时，逻辑电路在接收端激活电路模块的脉冲信号，以读取数据。 当读取存储在FIFO寄存器中的所有数据时，脉冲信号被关闭，从而在不影响数据传输效率的情况下降低脉冲信号消耗的功率，从而达到省电的目的。