发明申请
US20120295410A1 METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE
有权
用于制造具有减少的MILLER电容的超级电力装置的方法
- 专利标题: METHOD FOR FABRICATING SUPER-JUNCTION POWER DEVICE WITH REDUCED MILLER CAPACITANCE
- 专利标题(中): 用于制造具有减少的MILLER电容的超级电力装置的方法
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申请号: US13234132申请日: 2011-09-15
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公开(公告)号: US20120295410A1公开(公告)日: 2012-11-22
- 发明人: Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Yi-Chun Shih
- 申请人: Yung-Fa Lin , Shou-Yi Hsu , Meng-Wei Wu , Main-Gwo Chen , Yi-Chun Shih
- 优先权: TW100117647 20110519
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.
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