Invention Application
- Patent Title: Electrical Connection for Chip Scale Packaging
- Patent Title (中): 电子连接用于芯片级封装
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Application No.: US13152734Application Date: 2011-06-03
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Publication No.: US20120306070A1Publication Date: 2012-12-06
- Inventor: Ming-Chih Yew , Fu-Jen Li , Po-Yao Lin , Chia-Jen Cheng , Hsiu-Mei Yu
- Applicant: Ming-Chih Yew , Fu-Jen Li , Po-Yao Lin , Chia-Jen Cheng , Hsiu-Mei Yu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/485
- IPC: H01L23/485
Abstract:
A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.
Public/Granted literature
- US08624392B2 Electrical connection for chip scale packaging Public/Granted day:2014-01-07
Information query
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