Invention Application
US20120319073A1 VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME
有权
具有减少底部接触面积的可变电阻存储器件及其形成方法
- Patent Title: VARIABLE RESISTANCE MEMORY DEVICE HAVING REDUCED BOTTOM CONTACT AREA AND METHOD OF FORMING THE SAME
- Patent Title (中): 具有减少底部接触面积的可变电阻存储器件及其形成方法
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Application No.: US13591891Application Date: 2012-08-22
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Publication No.: US20120319073A1Publication Date: 2012-12-20
- Inventor: Hasan Nejad
- Applicant: Hasan Nejad
- Main IPC: H01L45/00
- IPC: H01L45/00
Abstract:
A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.
Public/Granted literature
- US08592797B2 Variable resistance memory device having reduced bottom contact area and method of forming the same Public/Granted day:2013-11-26
Information query
IPC分类:
