公开(公告)号：US20120319073A1

公开(公告)日：2012-12-20

申请号：US13591891

申请日：2012-08-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L45/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US07330367B2

公开(公告)日：2008-02-12

申请号：US11081652

申请日：2005-03-17

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C5/06

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US20060263979A1

公开(公告)日：2006-11-23

申请号：US11131994

申请日：2005-05-18

Applicant: Hasan Nejad ,  Gordon Haller ,  Thomas Figura ,  Ravi Iyer

Inventor： Hasan Nejad ,  Gordon Haller ,  Thomas Figura ,  Ravi Iyer

IPC: H01L21/8242 ,  H01L21/22 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/302 ,  H01L21/38

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L27/10897 ,  Y10S439/917

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract translation: 本发明包括形成与半导体结构相关的器件的方法。 在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

公开(公告)号：US07042749B2

公开(公告)日：2006-05-09

申请号：US10438344

申请日：2003-05-15

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/1659 ,  G11C11/1673 ,  G11C2213/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

公开(公告)号：US07023743B2

公开(公告)日：2006-04-04

申请号：US10784786

申请日：2004-02-24

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及在读取操作期间结合了交叉点和1T-1MTJ架构的某些优点的阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每列的​​多个堆叠列的读数 设置在相应的堆叠存储器层中。

公开(公告)号：US20050162883A1

公开(公告)日：2005-07-28

申请号：US10925243

申请日：2004-08-25

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/16 ,  G11C5/06 ,  G11C17/00

CPC classification number: G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract translation: 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US06879516B2

公开(公告)日：2005-04-12

申请号：US10784785

申请日：2004-02-24

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/14

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

公开(公告)号：US06735111B2

公开(公告)日：2004-05-11

申请号：US10051679

申请日：2002-01-16

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: G11C1100

CPC classification number: H01L27/222 ,  G11C11/16

Abstract: The invention includes a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit.

Abstract translation: 本发明包括具有存储器位堆栈的磁阻存储器件。 该堆叠包括在第一和第二磁性层之间的第一磁性层，第二磁性层和非磁性层。 第一导线靠近堆叠并被配置为用于从存储器位读取信息。 第一导线与第一或第二磁性层的欧姆连接。 第二导线与叠层隔开足够的距离，使得第二导线不被欧姆连接到堆叠，并被配置为用于将信息写入存储器位。

公开(公告)号：US06716644B2

公开(公告)日：2004-04-06

申请号：US10146890

申请日：2002-05-17

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H10L2100

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

公开(公告)号：US20090239366A1

公开(公告)日：2009-09-24

申请号：US12476364

申请日：2009-06-02

Applicant: Hasan Nejad ,  Thomas A. Figura ,  Gordon A. Haller ,  Ravi Iyer ,  John Mark Meldrim ,  Justin Harnish

Inventor： Hasan Nejad ,  Thomas A. Figura ,  Gordon A. Haller ,  Ravi Iyer ,  John Mark Meldrim ,  Justin Harnish

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/4975 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Abstract translation: 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。