A method of manufacturing a TFT, including forming a buffer layer, an amorphous silicon layer, an insulating layer, and a first conductive layer on a substrate, forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer, forming a semiconductor layer, a gate insulating layer, and a gate electrode that have a predetermined shape by simultaneously patterning the polycrystalline silicon layer, the insulating layer, and the first conductive layer, wherein the polycrystalline silicon layer is further etched to produce an undercut recessed a distance compared to sidewalls of the insulating layer and the first conductive layer, forming source and drain regions within the semiconductor layer by doping corresponding portions of the semiconductor layer, forming an interlayer insulating layer on the gate electrode, the interlayer insulating layer covering the gate insulating layer and forming source and drain electrodes that are electrically connected to source and drain regions respectively.