- 专利标题: ROUTING METHODS FOR INTEGRATED CIRCUIT DESIGNS
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申请号: US13559612申请日: 2012-07-27
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公开(公告)号: US20130031524A1公开(公告)日: 2013-01-31
- 发明人: Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
- 申请人: Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.