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公开(公告)号：US08365128B2
公开(公告)日：2013-01-29
申请号：US12347832
申请日：2008-12-31
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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公开(公告)号：US20090113372A1
公开(公告)日：2009-04-30
申请号：US12347902
申请日：2008-12-31
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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3.发明授权Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation 有权有条件地以不同的音调路由集成电路设计的一部分，以克服违反设计规则公开(公告)号：US08291365B2
公开(公告)日：2012-10-16
申请号：US11327226
申请日：2006-01-06
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 一种用于集成电路设计布局的创新布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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公开(公告)号：US20090113371A1
公开(公告)日：2009-04-30
申请号：US12347832
申请日：2008-12-31
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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公开(公告)号：US20130031524A1
公开(公告)日：2013-01-31
申请号：US13559612
申请日：2012-07-27
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
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公开(公告)号：US20060190897A1
公开(公告)日：2006-08-24
申请号：US11327226
申请日：2006-01-06
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 一种用于集成电路设计布局的创新布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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公开(公告)号：US07036101B2
公开(公告)日：2006-04-25
申请号：US10071862
申请日：2002-02-07
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
CPC分类号： G06F17/5077
摘要： An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
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公开(公告)号：US08255857B2
公开(公告)日：2012-08-28
申请号：US12347871
申请日：2008-12-31
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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公开(公告)号：US20090106728A1
公开(公告)日：2009-04-23
申请号：US12347871
申请日：2008-12-31
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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10.发明申请ROUTING INTERCONNECT OF INTEGRATED CIRCUIT DESIGNS WITH VARYING GRID DENSITIES 审中-公开集成电路设计的路由互连与变化的网络密度公开(公告)号：US20140215426A1
公开(公告)日：2014-07-31
申请号：US13753374
申请日：2013-01-29
申请人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
发明人： Limin He , So-Zen Yao , Wenyong Deng , Jing Chen , Liang-Jih Chao
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5018 , G06F17/5072
摘要： Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.
摘要翻译： 公开了集成电路设计布局的布线方法。 布局可以包括设计网表和库单元格。 多级全局路由可以为每个网络生成拓扑线。 可以执行设计上面向图形的基于图形的详细路由。 可以执行详细路由后的路由优化，以进一步提高路由质量。 一些方法可以是单线程的全部或部分时间，和/或多线程的一些或所有的时间。
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