Invention Application
US20130049808A1 High-Speed Level Shifter Between Low-Side Logic and High-Side Logic
有权
低端逻辑与高边逻辑之间的高速电平转换器
- Patent Title: High-Speed Level Shifter Between Low-Side Logic and High-Side Logic
- Patent Title (中): 低端逻辑与高边逻辑之间的高速电平转换器
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Application No.: US13222215Application Date: 2011-08-31
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Publication No.: US20130049808A1Publication Date: 2013-02-28
- Inventor: Georgi Panov
- Applicant: Georgi Panov
- Applicant Address: DE Neubiberg
- Assignee: Intel Mobile Communications GmbH
- Current Assignee: Intel Mobile Communications GmbH
- Current Assignee Address: DE Neubiberg
- Main IPC: H03K19/0175
- IPC: H03K19/0175
![High-Speed Level Shifter Between Low-Side Logic and High-Side Logic](/abs-image/US/2013/02/28/US20130049808A1/abs.jpg.150x150.jpg)
Abstract:
One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.
Public/Granted literature
- US08581627B2 High-speed level shifter between low-side logic and high-side logic Public/Granted day:2013-11-12
Information query
IPC分类: