公开(公告)号：US08633740B2

公开(公告)日：2014-01-21

申请号：US13227947

申请日：2011-09-08

申请人： Georgi Panov

发明人： Georgi Panov

IPC分类号： H03K4/06

CPC分类号： H03K4/066

摘要： One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).

摘要翻译： 本发明的一个实施例涉及一种波形发生器，其包括第一对电容器，第二对电容器，运放和控制逻辑。 运算放大器具有输入，并在其输出端提供差分三角波形作为输出信号。 控制逻辑包括电容器控制逻辑，斜坡控制逻辑，复位控制逻辑和充电控制逻辑。 电容器控制逻辑将电流对的第一和第二电容器连接到运算放大器的输入。 斜坡控制逻辑为当前对提供斜坡电流。 复位控制逻辑将下一对的电容复位到所选电压，例如零。 充电控制逻辑对下一对电容器进行充电，通常在下一对电容器被驱动到所选择的电压之后。

公开(公告)号：US20130063190A1

公开(公告)日：2013-03-14

申请号：US13227947

申请日：2011-09-08

申请人： Georgi Panov

发明人： Georgi Panov

IPC分类号： H03K4/06

CPC分类号： H03K4/066

摘要： One embodiment of the present invention relates to a waveform generator that includes a first pair of capacitors, a second pair of capacitors, an op amp and control logic. The op amp has inputs and provides a differential triangular waveform at its outputs as an output signal. The control logic includes capacitor control logic, ramp control logic, reset control logic and charge control logic. The capacitor control logic connects a current pair of the first and second capacitors to the inputs of the op amp. The ramp control logic provides ramp currents to the current pair. The reset control logic resets capacitors of a next pair to selected voltage(s), such as zero. The charge control logic charges the next pair of capacitors, typically after the next pair of capacitors has been driven to the selected voltage(s).

摘要翻译： 本发明的一个实施例涉及一种波形发生器，其包括第一对电容器，第二对电容器，运放和控制逻辑。 运算放大器具有输入，并在其输出端提供差分三角波形作为输出信号。 控制逻辑包括电容器控制逻辑，斜坡控制逻辑，复位控制逻辑和充电控制逻辑。 电容器控制逻辑将电流对的第一和第二电容器连接到运算放大器的输入。 斜坡控制逻辑为当前对提供斜坡电流。 复位控制逻辑将下一对的电容复位到所选电压，例如零。 充电控制逻辑对下一对电容器进行充电，通常在下一对电容器被驱动到所选择的电压之后。

公开(公告)号：US20140203876A1

公开(公告)日：2014-07-24

申请号：US13747553

申请日：2013-01-23

申请人： Georgi Panov ,  Rinaldo Zinke

发明人： Georgi Panov ,  Rinaldo Zinke

IPC分类号： H03F3/16

CPC分类号： H03F3/16 ,  H03F3/21 ,  H03F3/3022 ,  H03F3/45192

摘要： An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage.

摘要翻译： 描述了放大器电路，其包括第一场效应晶体管，其包括耦合到第一电源端的第一源极/漏极端子，耦合到放大器电路的输出的第二源极/漏极端子和栅极端子; 第二场效应晶体管，包括耦合到所述放大器电路的输入端的第一源极/漏极端子，耦合到所述第一场效应晶体管的栅极端子的第二源极/漏极端子和栅极端子; 第三场效应晶体管，包括耦合到所述放大器电路的第一偏置电流源的第一源极/漏极端子，耦合到其第一源极/漏极端子和第二场的栅极端子的第二源极/漏极端子和栅极端子 效应晶体管; 第四场效应晶体管，包括耦合到第二偏置电流源的第一源极/漏极端子，耦合到第二电源端子的第二源极/漏极端子和耦合到第三场效应晶体管的第二源极/漏极端子的栅极端子 ; 以及耦合到第四场效应晶体管的栅极的控制电路，其被配置为通过第四场效应晶体管的栅极来控制第四场效应晶体管的源极漏极电压等于参考电压。

公开(公告)号：US09344045B2

公开(公告)日：2016-05-17

申请号：US13904345

申请日：2013-05-29

申请人： Georgi Panov ,  Rinaldo Zinke

发明人： Georgi Panov ,  Rinaldo Zinke

IPC分类号： H03F3/38 ,  H03F3/217 ,  H03F3/187 ,  H03F3/45

CPC分类号： H03F3/217 ,  H03F3/187 ,  H03F3/45475

摘要： An amplifier includes a differential input with a positive and a negative input and an analog integrator with a differential integrator input and a differential integrator output. The analog integrator further includes an operational amplifier with a positive operational amplifier input, a negative operational amplifier input, a positive operational amplifier output and a negative operational amplifier output. The differential integrator input is coupled to the differential input. A ternary pulse width modulator includes two modulator inputs coupled to the differential integrator output and two modulator outputs. A first feedback path is coupled between a first of the two modulator outputs and the positive operational amplifier input and a second feedback path is coupled between a second of the two modulator outputs and the negative operational amplifier input. A first divert capacitor is coupled between the positive operational amplifier input and a constant voltage reference. A second divert capacitor is coupled between the negative operational amplifier input and the constant voltage reference.

摘要翻译： 放大器包括具有正和负输入的差分输入和具有差分积分器输入和差分积分器输出的模拟积分器。 模拟积分器还包括具有正运算放大器输入的运算放大器，负运算放大器输入，正运算放大器输出和负运算放大器输出。 差分积分器输入耦合到差分输入。 三进制脉宽调制器包括耦合到差分积分器输出和两个调制器输出的两个调制器输入。 第一反馈路径耦合在两个调制器输出中的第一个和正运算放大器输入之间，第二反馈路径耦合在两个调制器输出中的第二个和负运算放大器输入之间。 第一转换电容器耦合在正运算放大器输入和恒定电压基准之间。 第二转换电容器耦合在负运算放大器输入和恒定电压基准之间。

公开(公告)号：US08786366B1

公开(公告)日：2014-07-22

申请号：US13747553

申请日：2013-01-23

申请人： Georgi Panov ,  Rinaldo Zinke

发明人： Georgi Panov ,  Rinaldo Zinke

IPC分类号： H03F3/45

CPC分类号： H03F3/16 ,  H03F3/21 ,  H03F3/3022 ,  H03F3/45192

摘要： An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage.

摘要翻译： 描述了放大器电路，其包括第一场效应晶体管，其包括耦合到第一电源端的第一源极/漏极端子，耦合到放大器电路的输出的第二源极/漏极端子和栅极端子; 第二场效应晶体管，包括耦合到所述放大器电路的输入端的第一源极/漏极端子，耦合到所述第一场效应晶体管的栅极端子的第二源极/漏极端子和栅极端子; 第三场效应晶体管，包括耦合到放大器电路的第一偏置电流源的第一源极/漏极端子，耦合到其第一源极/漏极端子和第二场的栅极端子的第二源极/漏极端子和栅极端子 效应晶体管; 第四场效应晶体管，包括耦合到第二偏置电流源的第一源极/漏极端子，耦合到第二电源端子的第二源极/漏极端子和耦合到第三场效应晶体管的第二源极/漏极端子的栅极端子 ; 以及耦合到第四场效应晶体管的栅极的控制电路，其被配置为通过第四场效应晶体管的栅极来控制第四场效应晶体管的源极漏极电压等于参考电压。

公开(公告)号：US20130049808A1

公开(公告)日：2013-02-28

申请号：US13222215

申请日：2011-08-31

申请人： Georgi Panov

发明人： Georgi Panov

IPC分类号： H03K19/0175

CPC分类号： H03K19/018507 ,  H03K19/018521

摘要： One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.

摘要翻译： 本发明的一个实施例涉及一种具有可切换电流镜的电平转换器电路，其可以以互补方式选择性地激活和去激活以在逻辑侧之间转换差分输入信号（例如，为了平移在低侧接收的差分输入信号 到高端）。 闩锁连接到可切换电流镜的输出端。 锁存器被配置为从激活的电流镜接收转换的输出信号，并将另一个输出信号驱动到互补值。 锁存器还被配置为将转换后的输出信号提供给去激活（例如，关闭）激活的可切换电流镜的开关元件。 输出信号的存储允许电流镜保持停用，直到向电平移位器电路提供新的输入信号，从而允许降低电平转换器的静态功耗。

公开(公告)号：US20050195098A1

公开(公告)日：2005-09-08

申请号：US11036788

申请日：2005-01-14

申请人： Georgi Panov ,  Marco Bachhuber

发明人： Georgi Panov ,  Marco Bachhuber

IPC分类号： H03M1/74 ,  H03M1/76 ,  H03M1/78

CPC分类号： H03M1/682 ,  H03M1/765

摘要： Digital-to-analogue converter for converting a digital input signal into an analogue output signal includes a resistor string with switchable taps, a decoder circuit for connecting or disconnecting the taps in a manner dependent on the digital input signal, and a voltage divider. The voltage divider is operable to generate a divider voltage that divides a voltage difference that occurs between two connectable taps. The analogue output voltage is dependent on the divider voltage generated by the voltage divider.

摘要翻译： 用于将数字输入信号转换为模拟输出信号的数模转换器包括具有可切换抽头的电阻器串，用于以取决于数字输入信号的方式连接或断开抽头的解码器电路和分压器。 分压器可操作以产生分压电压，其分压在两个可连接的抽头之间发生的电压差。 模拟输出电压取决于分压器产生的分压电压。

公开(公告)号：US20140355790A1

公开(公告)日：2014-12-04

申请号：US13904345

申请日：2013-05-29

申请人： Georgi PANOV ,  Rinaldo Zinke

发明人： Georgi PANOV ,  Rinaldo Zinke

IPC分类号： H03F3/217 ,  H03F3/181 ,  H03F3/45

CPC分类号： H03F3/217 ,  H03F3/187 ,  H03F3/45475

摘要： An amplifier includes a differential input with a positive and a negative input and an analog integrator with a differential integrator input and a differential integrator output. The analog integrator further includes an operational amplifier with a positive operational amplifier input, a negative operational amplifier input, a positive operational amplifier output and a negative operational amplifier output. The differential integrator input is coupled to the differential input. A ternary pulse width modulator includes two modulator inputs coupled to the differential integrator output and two modulator outputs. A first feedback path is coupled between a first of the two modulator outputs and the positive operational amplifier input and a second feedback path is coupled between a second of the two modulator outputs and the negative operational amplifier input. A first divert capacitor is coupled between the positive operational amplifier input and a constant voltage reference. A second divert capacitor is coupled between the negative operational amplifier input and the constant voltage reference.

摘要翻译： 放大器包括具有正和负输入的差分输入和具有差分积分器输入和差分积分器输出的模拟积分器。 模拟积分器还包括具有正运算放大器输入的运算放大器，负运算放大器输入，正运算放大器输出和负运算放大器输出。 差分积分器输入耦合到差分输入。 三进制脉宽调制器包括耦合到差分积分器输出和两个调制器输出的两个调制器输入。 第一反馈路径耦合在两个调制器输出中的第一个和正运算放大器输入之间，第二反馈路径耦合在两个调制器输出中的第二个和负运算放大器输入之间。 第一转换电容器耦合在正运算放大器输入和恒定电压基准之间。 第二转换电容器耦合在负运算放大器输入和恒定电压基准之间。

公开(公告)号：US08581627B2

公开(公告)日：2013-11-12

申请号：US13222215

申请日：2011-08-31

申请人： Georgi Panov

发明人： Georgi Panov

IPC分类号： H03K19/0175

CPC分类号： H03K19/018507 ,  H03K19/018521

摘要： One embodiment of the present invention relates to a level shifter circuit having switchable current mirrors that can be selectively activated and deactivated in a complementary manner to translate differential input signals between logic sides (e.g., to translate a differential input signal received at a low-side to a high-side). A latch is connected to outputs of the switchable current mirrors. The latch is configured to receive a translated output signal from an activated current mirror and drive the other output signal to a complementary value. The latch is also configured to provide the translated output signal to a switching element that deactivates (e.g., turns off) the activated switchable current mirror. Storage of the output signals allows for the current mirrors to remain deactivated until a new input signal is provided to the level shifter circuit, thereby allowing for a reduction in the static power consumption of the level shifter.

摘要翻译： 本发明的一个实施例涉及一种具有可切换电流镜的电平转换器电路，其可以以互补方式选择性地激活和去激活以在逻辑侧之间转换差分输入信号（例如，为了平移在低侧接收的差分输入信号 到高端）。 闩锁连接到可切换电流镜的输出端。 锁存器被配置为从激活的电流镜接收转换的输出信号，并将另一个输出信号驱动到互补值。 锁存器还被配置为将转换后的输出信号提供给去激活（例如，关闭）激活的可切换电流镜的开关元件。 输出信号的存储允许电流镜保持停用，直到向电平移位器电路提供新的输入信号，从而允许降低电平转换器的静态功耗。

公开(公告)号：US20080284393A1

公开(公告)日：2008-11-20

申请号：US11748423

申请日：2007-05-14

申请人： Georgi Panov ,  Ettore Riccio

发明人： Georgi Panov ,  Ettore Riccio

IPC分类号： G05F1/56

CPC分类号： G05F1/56

摘要： Implementations related to low drop output (LDO) circuit arrangements are presented herein.

摘要翻译： 本文给出了与低压降输出（LDO）电路布置有关的实现。