发明申请
- 专利标题： ENHANCED WAFER TEST LINE STRUCTURE
- 专利标题（中）： 增强型测试线结构
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申请号： US13246536申请日： 2011-09-27
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公开(公告)号： US20130075725A1公开(公告)日： 2013-03-28
- 发明人: Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
- 申请人： Jiun-Jie Huang , Chi-Yen Lin , Ling-Sung Wang
- 申请人地址： TW Hsin-Chu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址： TW Hsin-Chu
- 主分类号： H01L23/52
- IPC分类号： H01L23/52 ; H01L21/66
摘要：
A semiconductor wafer has a die area and a scribe area. A first dummy pad is formed in a first test line area of the scribe area and filled with a first material as part of a first metal layer. A first interlayer dielectric is formed over the first metal layer. A first interconnect pattern is formed in the die area and above the first interlayer dielectric, and a first trench pattern is formed in the first test line area of the scribe area and above the interlayer dielectric. The first interconnect pattern and the first trench pattern are filled with a second metal layer, and the first trench pattern is aligned above the first dummy pad. An enhanced test line structure including the first trench pattern and the first dummy pad is formed and probed in a back end of line (BEOL) process.
公开/授权文献
- US08476629B2 Enhanced wafer test line structure 公开/授权日：2013-07-02
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