A memory cell array of a first semiconductor chip includes a normal cell array and a spare cell array. A first defect address data storage circuit outputs first defect address data indicating an address of a defective memory cell in the memory cell array. A first comparison circuit compares address data with the first defect address data and outputs a first match signal in case of matching. A second defect address data storage circuit outputs second defect address data indicating an address of a defective memory cell in the memory cell array. A second comparison circuit compares the address data with the second defect address data and outputs a second match signal in case of matching.