发明申请
US20130117536A1 RECONFIGURABLE INSTRUCTION ENCODING METHOD AND PROCESSOR ARCHITECTURE 有权
可重构指令编码方法和处理器架构

RECONFIGURABLE INSTRUCTION ENCODING METHOD AND PROCESSOR ARCHITECTURE
摘要:
A reconfigurable instruction encoding method includes the followings. An instruction distribution of an application is counted, and multiple instruction pairs with higher utilization rates are accordingly found. Multiple instructions of the instruction pairs are duplicately encoded according to multiple reserved sections of an original instruction table, so that the instructions have corresponding reconfigured codes and a reconfigured instruction table extended from the original instruction table and including the reconfigured codes is obtained. A compiler is utilized to generate multiple machine codes according to the reconfigured instruction table and consecutive execution instructions. Hamming distance of the machine codes corresponding to the reconfigured instruction table and the execution instructions are not longer than Hamming distance of the machine codes generated according to the original instruction table and the execution instructions.
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