Invention Application
- Patent Title: Method for Forming Chip-on-Wafer Assembly
- Patent Title (中): 晶圆芯片组装方法
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Application No.: US13298126Application Date: 2011-11-16
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Publication No.: US20130119552A1Publication Date: 2013-05-16
- Inventor: Jing-Cheng Lin , Cheng-Lin Huang , Szu Wei Lu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu
- Applicant: Jing-Cheng Lin , Cheng-Lin Huang , Szu Wei Lu , Jui-Pin Hung , Shin-Puu Jeng , Chen-Hua Yu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/56
Abstract:
A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.
Public/Granted literature
- US08779599B2 Packages including active dies and dummy dies and methods for forming the same Public/Granted day:2014-07-15
Information query
IPC分类:
