发明申请
- 专利标题: MULTI-LEVEL INSTRUCTION CACHE PREFETCHING
- 专利标题(中): 多级指导高速缓存
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申请号: US13312962申请日: 2011-12-06
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公开(公告)号: US20130145102A1公开(公告)日: 2013-06-06
- 发明人: Nicholas Wang , Jack Hilaire Choquette
- 申请人: Nicholas Wang , Jack Hilaire Choquette
- 主分类号: G06F12/02
- IPC分类号: G06F12/02
摘要:
One embodiment of the present invention sets forth an improved way to prefetch instructions in a multi-level cache. Fetch unit initiates a prefetch operation to transfer one of a set of multiple cache lines, based on a function of a pseudorandom number generator and the sector corresponding to the current instruction L1 cache line. The fetch unit selects a prefetch target from the set of multiple cache lines according to some probability function. If the current instruction L1 cache 370 is located within the first sector of the corresponding L1.5 cache line, then the selected prefetch target is located at a sector within the next L1.5 cache line. The result is that the instruction L1 cache hit rate is improved and instruction fetch latency is reduced, even where the processor consumes instructions in the instruction L1 cache at a fast rate.
公开/授权文献
- US09110810B2 Multi-level instruction cache prefetching 公开/授权日:2015-08-18
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