利索-全球专利检索

  1. 登录
  2. 注册
发明申请
US20130145227A1 Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port 有权
用于减少存储器中的错误检测/校正位数量的数据保护处理器端口的方法和装置

Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port
摘要：
An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
摘要（中）：

用于接口处理设备和存储设备的接口设备包括纠错码（ECC）编码器，用于计算ECC比特，并且至少部分地基于由所述处理设备提供的数据，向处理设备提供ECC比特 存储器件，从而不需要将ECC位存储在存储器件中。 接口设备可以包括奇偶校验编码器，以根据由处理设备提供的数据提供奇偶校验位到存储器设备;以及奇偶解码器，用于根据数据有选择地修改ECC位， 奇偶校验位由存储器件提供。 ECC编码器可以提供ECC位，并且奇偶校验解码器可以基于由存储器件提供的数据和由存储器件提供的奇偶校验位来选择性地修改提供给处理器件的ECC位。

公开/授权文献
信息查询
Global Dossier Espacenet
0/0