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1.发明授权Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port 有权用于减少与数据保护的处理器端口耦合的存储器中的错误检测/校正位的量的方法和装置公开(公告)号：US08707133B2
公开(公告)日：2014-04-22
申请号：US13311102
申请日：2011-12-05
CPC分类号： G06F11/10 , G06F11/1048 , G06F13/14 , H03M13/19 , H03M13/3776
摘要： An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
摘要翻译： 用于接口处理设备和存储设备的接口设备包括纠错码（ECC）编码器，用于计算ECC比特，并且至少部分地基于由所述处理设备提供的数据，向处理设备提供ECC比特 存储器件，从而不需要将ECC位存储在存储器件中。 接口设备可以包括奇偶校验编码器，以根据由处理设备提供的数据提供奇偶校验位到存储器设备;以及奇偶解码器，用于根据数据有选择地修改ECC位， 奇偶校验位由存储器件提供。 ECC编码器可以提供ECC位，并且奇偶校验解码器可以基于由存储器件提供的数据和由存储器件提供的奇偶校验位来选择性地修改提供给处理器件的ECC位。
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2.发明申请Method and Apparatus to Reduce a Quantity of Error Detection/Correction Bits in Memory Coupled to a Data-Protected Processor Port 有权用于减少存储器中的错误检测/校正位数量的数据保护处理器端口的方法和装置公开(公告)号：US20130145227A1
公开(公告)日：2013-06-06
申请号：US13311102
申请日：2011-12-05
CPC分类号： G06F11/10 , G06F11/1048 , G06F13/14 , H03M13/19 , H03M13/3776
摘要： An interface device to interface a processing device and a memory device includes an error correcting code (ECC) encoder to calculate ECC bit(s) and to provide the ECC bit(s) to the processing device based at least in part on data provided by the memory device, thereby eliminating a need to store the ECC bits in the memory device. The interface device may include a parity encoder to provide parity bit(s) to the memory device as a function of data provided by the processing device, and a parity decoder to selectively modify the ECC bit(s) as a function of the data and parity bit(s) provided by the memory device. The ECC encoder may provide ECC bits, and the parity decoder may selectively modify the ECC bits provided to the processing device based on data provided by the memory device and parity bit(s) provided by the memory device.
摘要翻译： 用于接口处理设备和存储设备的接口设备包括纠错码（ECC）编码器，用于计算ECC比特，并且至少部分地基于由所述处理设备提供的数据，向处理设备提供ECC比特 存储器件，从而不需要将ECC位存储在存储器件中。 接口设备可以包括奇偶校验编码器，以根据由处理设备提供的数据提供奇偶校验位到存储器设备;以及奇偶解码器，用于根据数据有选择地修改ECC位， 奇偶校验位由存储器件提供。 ECC编码器可以提供ECC位，并且奇偶校验解码器可以基于由存储器件提供的数据和由存储器件提供的奇偶校验位来选择性地修改提供给处理器件的ECC位。
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公开(公告)号：US08724745B2
公开(公告)日：2014-05-13
申请号：US12869820
申请日：2010-08-27
IPC分类号： H04L27/06
CPC分类号： H04L25/4927 , H04L7/042 , H04L7/10 , H04L25/4904
摘要： A system and method for decoding coded data streams is disclosed. In one embodiment, in a method for decoding coded data streams, a coded data stream including an embedded input clock signal is oversampled to measure substantially sequentially a plurality of pulse widths in a current frame using a sync and reference value acquisition digital logic. The coded data steam includes a plurality of frames, and each frame includes a preamble of fixed length and a series of data bits. The oversampling is performed using a high frequency clock signal having a substantially higher frequency than a frequency of the embedded input clock signal. Then, the coded data stream is decoded based on the measured plurality of pulse widths in the current frame using a data decoder.
摘要翻译： 公开了一种用于解码编码数据流的系统和方法。 在一个实施例中，在用于解码编码数据流的方法中，包括嵌入式输入时钟信号的编码数据流被过采样，以使用同步和参考值采集数字逻辑基本顺序地测量当前帧中的多个脉冲宽度。 编码数据蒸汽包括多个帧，并且每个帧包括固定长度的前同步码和一系列数据位。 使用具有比嵌入的输入时钟信号的频率更高的频率的高频时钟信号来执行过采样。 然后，使用数据解码器，基于当前帧中测量的多个脉冲宽度对编码数据流进行解码。
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4.发明授权Method and apparatus for power management control of an embedded memory having sleep and shutdown features 有权具有睡眠和关机功能的嵌入式存储器的功率管理控制方法和装置公开(公告)号：US08713340B2
公开(公告)日：2014-04-29
申请号：US13271640
申请日：2011-10-12
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G11C8/06 , G11C8/18 , Y02D10/13 , Y02D10/14
摘要： A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.
摘要翻译： 功率管理控制器控制与存储器件相关联的功率模式，并且包括可操作以提供功率模式控制信号的逻辑元件。 逻辑元件响应于第一和第二控制信号，第二控制信号是第一控制信号的延迟版本。 第一控制信号由处理设备提供，并且功率模式控制信号在芯片选择信号转换为有效之前转换（i）不活动，和/或（ii）在芯片选择信号转变为不活动之后激活。 芯片选择信号控制存储器件，并且功率模式控制信号控制与存储器件相关联的功率模式。 还公开了相应的方法，计算机可读介质和电子系统。 还公开了一种选择与控制与存储器件相关联的功率模式的功率管理控制器相关联的功率控制模式的方法。
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公开(公告)号：US08904221B2
公开(公告)日：2014-12-02
申请号：US13334885
申请日：2011-12-22
CPC分类号： G06F1/12
摘要： A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.
摘要翻译： 数据处理系统包括根据第一时钟信号操作的处理器和根据第二时钟信号操作的存储器。 数据处理系统使得处理器至少部分地响应于来自第一同步电路的信号和来自第二同步电路的信号从存储器读取数据。 第一同步电路包括第一存储元件，其对与第二时钟信号同步的信号与对第一存储元件的输出进行采样的第二存储元件组合进行采样。 第一和第二存储元件由第一时钟信号中的反向转换触发。 第二同步电路包括以类似方式配置的第三和第四存储元件，除了它们对与第一时钟信号同步的信号进行采样，并且由第二时钟信号中的反向转换触发。
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公开(公告)号：US20130332763A1
公开(公告)日：2013-12-12
申请号：US13493081
申请日：2012-06-11
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G11C5/148 , Y02D10/14
摘要： A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
摘要翻译： 存储器件包括一个或多个电源门和状态信号电路。 一个或多个功率门中的每一个都是可配置的，使得存储器件的相应部分被断电。 状态信号电路可操作以产生指示何时配置一个或多个电源门以使得存储器件完全通电的电源状态输出信号。
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7.发明申请Method and Apparatus for Power Management Control of an Embedded Memory Having Sleep and Shutdown Features 有权具有睡眠和关机功能的嵌入式存储器的电源管理控制方法和装置公开(公告)号：US20130097445A1
公开(公告)日：2013-04-18
申请号：US13271640
申请日：2011-10-12
CPC分类号： G06F1/3275 , G11C8/06 , G11C8/18 , Y02D10/13 , Y02D10/14
摘要： A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.
摘要翻译： 功率管理控制器控制与存储器件相关联的功率模式，并且包括可操作以提供功率模式控制信号的逻辑元件。 逻辑元件响应于第一和第二控制信号，第二控制信号是第一控制信号的延迟版本。 第一控制信号由处理设备提供，并且功率模式控制信号在芯片选择信号转换为有效之前转换（i）不活动，和/或（ii）在芯片选择信号转变为不活动之后激活。 芯片选择信号控制存储器件，并且功率模式控制信号控制与存储器件相关联的功率模式。 还公开了相应的方法，计算机可读介质和电子系统。 还公开了一种选择与控制与存储器件相关联的功率模式的功率管理控制器相关联的功率控制模式的方法。
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公开(公告)号：US08947966B2
公开(公告)日：2015-02-03
申请号：US13493081
申请日：2012-06-11
IPC分类号： G11C5/14
CPC分类号： G06F1/3275 , G11C5/148 , Y02D10/14
摘要： A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
摘要翻译： 存储器件包括一个或多个电源门和状态信号电路。 一个或多个功率门中的每一个都是可配置的，使得存储器件的相应部分被断电。 状态信号电路可操作以产生指示何时配置一个或多个电源门以使得存储器件完全通电的电源状态输出信号。
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公开(公告)号：US20130166938A1
公开(公告)日：2013-06-27
申请号：US13334885
申请日：2011-12-22
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor to read data from the memory at least in part in response to a signal from first synchronizing circuitry and a signal from second synchronizing circuitry. The first synchronizing circuitry comprises a first storage element that samples a signal synchronized to the second clock signal in combination with a second storage element that samples an output of the first storage element. The first and second storage elements are triggered by inverse transitions in the first clock signal. The second synchronizing circuitry comprises third and fourth storage elements configured in a similar manner, except that they sample a signal synchronized to the first clock signal and are triggered by inverse transitions in the second clock signal.
摘要翻译： 数据处理系统包括根据第一时钟信号操作的处理器和根据第二时钟信号操作的存储器。 数据处理系统使得处理器至少部分地响应于来自第一同步电路的信号和来自第二同步电路的信号从存储器读取数据。 第一同步电路包括第一存储元件，其对与第二时钟信号同步的信号与对第一存储元件的输出进行采样的第二存储元件组合进行采样。 第一和第二存储元件由第一时钟信号中的反向转换触发。 第二同步电路包括以类似方式配置的第三和第四存储元件，除了它们对与第一时钟信号同步的信号进行采样，并且由第二时钟信号中的反向转换触发。
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公开(公告)号：US20120051465A1
公开(公告)日：2012-03-01
申请号：US12869820
申请日：2010-08-27
IPC分类号： H04L27/06
CPC分类号： H04L25/4927 , H04L7/042 , H04L7/10 , H04L25/4904
摘要： A system and method for decoding coded data streams is disclosed. In one embodiment, in a method for decoding coded data streams, a coded data stream including an embedded input clock signal is oversampled to measure substantially sequentially a plurality of pulse widths in a current frame using a sync and reference value acquisition digital logic. The coded data steam includes a plurality of frames, and each frame includes a preamble of fixed length and a series of data bits. The oversampling is performed using a high frequency clock signal having a substantially higher frequency than a frequency of the embedded input clock signal. Then, the coded data stream is decoded based on the measured plurality of pulse widths in the current frame using a data decoder.
摘要翻译： 公开了一种用于解码编码数据流的系统和方法。 在一个实施例中，在用于解码编码数据流的方法中，包括嵌入式输入时钟信号的编码数据流被过采样，以使用同步和参考值采集数字逻辑基本顺序地测量当前帧中的多个脉冲宽度。 编码数据蒸汽包括多个帧，并且每个帧包括固定长度的前同步码和一系列数据位。 使用具有比嵌入的输入时钟信号的频率更高的频率的高频时钟信号来执行过采样。 然后，使用数据解码器，基于当前帧中测量的多个脉冲宽度对编码数据流进行解码。
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