Invention Application
- Patent Title: Delay Locked Loop Circuit and Method
- Patent Title (中): 延迟锁定回路电路及方法
-
Application No.: US13718783Application Date: 2012-12-18
-
Publication No.: US20130176061A1Publication Date: 2013-07-11
- Inventor: Dieter Haerle , Tony Mai , Peter Vlasenko
- Applicant: MOSAID Technologies Incorporated
- Applicant Address: CA Ottawa
- Assignee: MOSAID Technologies Incorporated
- Current Assignee: MOSAID Technologies Incorporated
- Current Assignee Address: CA Ottawa
- Main IPC: H03L7/10
- IPC: H03L7/10

Abstract:
A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
Public/Granted literature
- US08704569B2 Delay locked loop circuit and method Public/Granted day:2014-04-22
Information query