发明申请
- 专利标题: ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD
- 专利标题(中): 对准耐磨半导体接触和方法
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申请号: US13364976申请日: 2012-02-02
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公开(公告)号: US20130200471A1公开(公告)日: 2013-08-08
- 发明人: André P. Labonté , Richard S. Wise
- 申请人: André P. Labonté , Richard S. Wise
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人: GLOBALFOUNDRIES INC.
- 当前专利权人地址: KY Grand Cayman
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/768
摘要:
An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region.
公开/授权文献
- US08507375B1 Alignment tolerant semiconductor contact and method 公开/授权日:2013-08-13
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