发明申请
US20130201760A1 Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory
有权
在3D非易失性存储器中减少弱擦除类型读取干扰
- 专利标题: Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory
- 专利标题(中): 在3D非易失性存储器中减少弱擦除类型读取干扰
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申请号: US13364518申请日: 2012-02-02
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公开(公告)号: US20130201760A1公开(公告)日: 2013-08-08
- 发明人: Yingda Dong , Man L. Mui , Hitoshi Miwa
- 申请人: Yingda Dong , Man L. Mui , Hitoshi Miwa
- 主分类号: G11C16/26
- IPC分类号: G11C16/26 ; G11C16/04
摘要:
A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.