公开(公告)号：US20130201760A1

公开(公告)日：2013-08-08

申请号：US13364518

申请日：2012-02-02

申请人： Yingda Dong ,  Man L. Mui ,  Hitoshi Miwa

发明人： Yingda Dong ,  Man L. Mui ,  Hitoshi Miwa

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/1157 ,  H01L27/11582

摘要： A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

摘要翻译： 用于3D堆叠存储器件的读取处理为未选择的存储器串提供最佳级别的通道升压，以抑制正常和弱擦除类型的读取干扰。 通过控制位线（Vbl），漏极侧选择栅极（Vsgd_unsel），源极选择栅极（Vsgs_unsel），存储器件的选定电平（字线层）（Vcg_sel）的电压，以及 未选择的内存设备级别（Vcg_unsel）。 通过初始使漏极侧和源极选择栅极不导通，可以提高通道，以允许来自增加的Vcg_unsel的电容耦合。 然后通过升高Vsgd_unsel和/或Vsgs_unsel使漏极侧和/或源极侧选择栅极变得不导通，从而中断升压。 此外，当Vcg_unsel仍在增加时，通过使漏极侧和/或源极选择栅极再次导通，可以发生升压。 或者，通道可以在Vbl驱动。 两级升压驱动Vbl上的通道，然后通过电容耦合提供升压。

公开(公告)号：US20090290429A1

公开(公告)日：2009-11-26

申请号：US12126375

申请日：2008-05-23

申请人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427

摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.

摘要翻译： 在非易失性存储器中改善通道增强以减少程序干扰。 预充电模块电压源用于在编程操作期间对位线进行预充电。 预充电模块电压源通过位线耦合到衬底通道以升高通道。 通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。 为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。 导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

公开(公告)号：US07719902B2

公开(公告)日：2010-05-18

申请号：US12126375

申请日：2008-05-23

申请人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Man L. Mui ,  Jeffrey W. Lutze ,  Shinji Sato ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427

摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.

摘要翻译： 在非易失性存储器中改善通道增强以减少程序干扰。 预充电模块电压源用于在编程操作期间对位线进行预充电。 预充电模块电压源通过位线耦合到衬底通道以升高通道。 通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。 为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。 导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

公开(公告)号：US08867271B2

公开(公告)日：2014-10-21

申请号：US13484088

申请日：2012-05-30

申请人： Haibo Li ,  Xiying Costa ,  Masaaki Higashitani ,  Man L. Mui

发明人： Haibo Li ,  Xiying Costa ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C29/025 ,  G11C29/028

摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.

摘要翻译： 在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。 为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。 具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。 可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。 重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。 方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

公开(公告)号：US08429330B2

公开(公告)日：2013-04-23

申请号：US12209697

申请日：2008-09-12

申请人： Jun Wan ,  Yupin K. Fong ,  Man L. Mui

发明人： Jun Wan ,  Yupin K. Fong ,  Man L. Mui

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1032

摘要： A method in which data is randomized before being stored in a non-volatile memory to minimize data pattern-related read failures. Predetermined randomized non-user data is stored in a block or other location of a memory array, and accessed as needed by a memory device controller to randomize user data before it is stored in other blocks of the array. Each portion of the user data which is stored in a block is randomized using a portion of the non-user data which is stored in the same relative location in another block.

摘要翻译： 数据在被存储在非易失性存储器中之前被随机化以最小化数据模式相关读取故障的方法。 预定的随机非用户数据存储在存储器阵列的块或其他位置中，并且由存储器件控制器根据需要进行访问，以便在将用户数据存储在阵列的其他块之前随机化。 使用存储在另一块中相同相对位置的非用户数据的一部分来随机化存储在块中的用户数据的每个部分。

公开(公告)号：US20100070682A1

公开(公告)日：2010-03-18

申请号：US12209708

申请日：2008-09-12

申请人： Jun Wan ,  Yupin K. Fong ,  Man L. Mui

发明人： Jun Wan ,  Yupin K. Fong ,  Man L. Mui

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1032

摘要： A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided.

摘要翻译： 一种非易失性存储器，其中数据在被存储在非易失性存储器中之前被随机化以最小化与数据模式相关的读取故障。 使用存储器管芯上的电路执行随机化，使得存储器管芯相对于外部的片外控制器是便携式的。 存储器上的电路根据使用根据写入地址移位的种子生成的密钥对用户数据进行加扰。 还提供了相应的片上解扰。

公开(公告)号：US20130279257A1

公开(公告)日：2013-10-24

申请号：US13450313

申请日：2012-04-18

申请人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

发明人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C16/04

CPC分类号： G11C16/14 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3445 ,  G11C16/3472 ,  H01L27/1157 ,  H01L27/11582

摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

公开(公告)号：US20110188317A1

公开(公告)日：2011-08-04

申请号：US12697017

申请日：2010-01-29

申请人： Man L. Mui ,  Pao-Ling Koh ,  Tien-Chien Kuo ,  Khanh T. Nguyen

发明人： Man L. Mui ,  Pao-Ling Koh ,  Tien-Chien Kuo ,  Khanh T. Nguyen

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5642

摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.

摘要翻译： 在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。 感测模块​​与每个存储元件相关联。 基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。 管理电路不需要访问写入数据，以确定“0”是否表示完成编程的存储元件。 通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

公开(公告)号：US08787094B2

公开(公告)日：2014-07-22

申请号：US13450294

申请日：2012-04-18

申请人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

发明人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C11/34 ,  G11C16/14 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3445 ,  G11C5/02 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3472 ,  G11C29/52 ,  H01L27/11582 ,  H01L29/7926

摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.

摘要翻译： 对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。 结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。 可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。 对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。 对于字线子集，字线电压浮动以禁止擦除。 可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障位。

公开(公告)号：US20130279256A1

公开(公告)日：2013-10-24

申请号：US13450294

申请日：2012-04-18

申请人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

发明人： Xiying Costa ,  Haibo Li ,  Masaaki Higashitani ,  Man L. Mui

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C5/02 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3472 ,  G11C29/52 ,  H01L27/11582 ,  H01L29/7926

摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.

摘要翻译： 对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。 结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。 可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。 对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。 对于字线子集，字线电压浮动以禁止擦除。 可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。