发明申请
US20130326446A1 TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES
有权
检查设备的计算机辅助设计层的技术，以减少错误的规则规则的发生
- 专利标题： TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES
- 专利标题（中）： 检查设备的计算机辅助设计层的技术，以减少错误的规则规则的发生
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申请号： US13484022申请日： 2012-05-30
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公开(公告)号： US20130326446A1公开(公告)日： 2013-12-05
- 发明人: Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
- 申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
- 申请人地址： US TX Austin
- 专利权人： FREESCALE SEMICONDUCTOR, INC.
- 当前专利权人： FREESCALE SEMICONDUCTOR, INC.
- 当前专利权人地址： US TX Austin
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.