发明申请
US20130329512A1 CLOCKED MEMORY WITH WORD LINE ACTIVATION DURING A FIRST PORTION OF THE CLOCK CYCLE
有权
在时钟周期的第一部分中使用字线激活的时钟记忆
- 专利标题： CLOCKED MEMORY WITH WORD LINE ACTIVATION DURING A FIRST PORTION OF THE CLOCK CYCLE
- 专利标题（中）： 在时钟周期的第一部分中使用字线激活的时钟记忆
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申请号： US13491722申请日： 2012-06-08
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公开(公告)号： US20130329512A1公开(公告)日： 2013-12-12
- 发明人: HEMA RAMAMURTHY , RAVINDRARAJ RAMARAJU
- 申请人： HEMA RAMAMURTHY , RAVINDRARAJ RAMARAJU
- 主分类号： G11C8/10
- IPC分类号： G11C8/10
摘要：
A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
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