发明申请
- 专利标题: CIRCUIT SHARING TIME DELAY INTEGRATOR
- 专利标题(中): 电路共享时间延迟整合器
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申请号: US13594559申请日: 2012-08-24
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公开(公告)号: US20130335132A1公开(公告)日: 2013-12-19
- 发明人: Chin-Fong CHIU , Hann-Huei TSAI , Wen-Hsu CHANG , Chih-Cheng HSIEH , Kuo-Wei CHENG
- 申请人: Chin-Fong CHIU , Hann-Huei TSAI , Wen-Hsu CHANG , Chih-Cheng HSIEH , Kuo-Wei CHENG
- 申请人地址: TW Hsinchu City
- 专利权人: National Applied Research Laboratories
- 当前专利权人: National Applied Research Laboratories
- 当前专利权人地址: TW Hsinchu City
- 优先权: TW101121184 20120613
- 主分类号: G06G7/18
- IPC分类号: G06G7/18
摘要:
The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.
公开/授权文献
- US08704580B2 Circuit sharing time delay integrator 公开/授权日:2014-04-22