公开(公告)号：US20130335132A1

公开(公告)日：2013-12-19

申请号：US13594559

申请日：2012-08-24

申请人： Chin-Fong CHIU ,  Hann-Huei TSAI ,  Wen-Hsu CHANG ,  Chih-Cheng HSIEH ,  Kuo-Wei CHENG

发明人： Chin-Fong CHIU ,  Hann-Huei TSAI ,  Wen-Hsu CHANG ,  Chih-Cheng HSIEH ,  Kuo-Wei CHENG

IPC分类号： G06G7/18

CPC分类号： G06G7/18 ,  H04N5/3743 ,  H04N5/37457

摘要： The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.

摘要翻译： 本发明公开了一种电路共享时延积分器结构。 该电路共享时延积分器结构的主要组成要素是共享电路，第一控制块，多个第二控制块和由定时发生器电路产生的定时集。 共享电路可以是OP-AMP，有源负载或用于信号积累应用中的各种组合中的任何一种。 通过本发明实现信号积累的应用，消除了加法器电路的必要性，大大降低了整体电路和因此产生集成电路所需的晶体管总量，从而大大降低了成本 定时和功率效率都可以实现。