发明申请
US20130339622A1 CACHE COHERENCY PROTOCOL FOR ALLOWING PARALLEL DATA FETCHES AND EVICTION TO THE SAME ADDRESSABLE INDEX
有权
用于允许并行数据存储器的缓存协议和相同可寻址索引的错误
- 专利标题: CACHE COHERENCY PROTOCOL FOR ALLOWING PARALLEL DATA FETCHES AND EVICTION TO THE SAME ADDRESSABLE INDEX
- 专利标题(中): 用于允许并行数据存储器的缓存协议和相同可寻址索引的错误
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申请号: US13523535申请日: 2012-06-14
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公开(公告)号: US20130339622A1公开(公告)日: 2013-12-19
- 发明人: Ekaterina M. Ambroladze , Michael Blake , Tim Bronson , Garrett Drapala , Pak-kin Mak , Arthur J. O'Neill
- 申请人: Ekaterina M. Ambroladze , Michael Blake , Tim Bronson , Garrett Drapala , Pak-kin Mak , Arthur J. O'Neill
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F12/08
- IPC分类号: G06F12/08
摘要:
A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.
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