公开(公告)号：US09003125B2

公开(公告)日：2015-04-07

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US20130339622A1

公开(公告)日：2013-12-19

申请号：US13523535

申请日：2012-06-14

申请人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

发明人： Ekaterina M. Ambroladze ,  Michael Blake ,  Tim Bronson ,  Garrett Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC分类号： G06F12/08

CPC分类号： G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

摘要： A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

摘要翻译： 提供了高速缓存一致性技术。 高速缓存控制器基于第一事务的高速缓存未命中从一个等同类中的多个集合中选择第一集合，并且将锁定放置在整个一致类中，其中锁定防止其他事务访问同余类。 高速缓存控制器在高速缓存目录中指定具有指示第一事务在第一集合上工作的标记位的第一集合，并且第一集合的标记位阻止其他事务访问同余类中的第一集合。 高速缓存控制器基于为第一组指定的标记位移除同余类上的锁，并且基于在一致类中的第一集合上的第一次交易完成工作将第一组的标记位重置为未标记位 。

公开(公告)号：US08250308B2

公开(公告)日：2012-08-21

申请号：US12031977

申请日：2008-02-15

申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership state of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权状态，将目标行的状态返回到请求节点并形成组合响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

公开(公告)号：US20090210626A1

公开(公告)日：2009-08-20

申请号：US12031977

申请日：2008-02-15

申请人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Ekaterina M. Ambroladze ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Craig R. Waters

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： The method includes initiating a processor request to a cache in a requesting node and broadcasting the processor request to remote nodes when the processor request encounters a local cache miss, performing a directory search of each remote cache to determine a state of a target line's address and an ownership slate of a specified address, returning the state of the target line to the requesting node and forming a combined response, and broadcasting the combined response to each remote node. During a fetch operation, when the directory search indicates an IM or a Target Memory node on a remote node, data is sourced from the respective remote cache and forwarded to the requesting node while protecting the data, and during a store operation, the data is sourced from the requesting node and protected while being forwarded to the IM or the Target Memory node after coherency has been established.

摘要翻译： 该方法包括：当处理器请求遇到本地高速缓存未命中时，向请求节点中的高速缓存发起处理器请求并将处理器请求广播到远程节点，执行每个远程高速缓存的目录搜索以确定目标行的地址的状态，以及 指定地址的所有权，将目标行的状态返回到请求节点并形成组合的响应，并将组合的响应广播到每个远程节点。 在获取操作期间，当目录搜索指示远程节点上的IM或目标存储器节点时，数据来自相应的远程高速缓存并且在保护数据的同时被转发到请求节点，并且在存储操作期间，数据是 源自请求节点，并且在一致性被建立之后被转发到IM或目标存储器节点时被保护。

公开(公告)号：US20090210629A1

公开(公告)日：2009-08-20

申请号：US12032058

申请日：2008-02-15

申请人： Michael A. Blake ,  Christine C. Jones ,  Pak-kin Mak ,  Arthur J. O'Neill, JR.

发明人： Michael A. Blake ,  Christine C. Jones ,  Pak-kin Mak ,  Arthur J. O'Neill, JR.

IPC分类号： G06F12/08

CPC分类号： G06F12/0817

摘要： A method, system and computer program product for selectively purging entries in a cache of a computer system. The method includes determining a starting storage address and a length of the storage address range to be purged, determining preset values for a congruence class and a compartment of a cache directory, accessing the cache directory based on the preset value of the congruence class, and selecting an entry in the cache directory based on the preset value of the compartment, determining validity of the entry accessed by examining an ownership tag of the entry, comparing a line address of the entry with the starting storage address and a sum of the starting storage address and the length of the storage address range, and selectively purging the entry based on the comparison result.

摘要翻译： 一种用于选择性地清除计算机系统的高速缓存中的条目的方法，系统和计算机程序产品。 该方法包括确定要清除的存储地址范围的起始存储地址和长度，确定高速缓存目录的同余类和隔间的预设值，基于同余类的预设值访问高速缓存目录;以及 基于所述隔室的所述预设值来选择所述缓存目录中的条目，通过检查所述条目的所有权标签来确定所访问的条目的有效性，将所述条目的行地址与所述起始存储地址进行比较，以及所述起始存储器 地址和存储地址范围的长度，并且基于比较结果选择性地清除条目。

公开(公告)号：US08180970B2

公开(公告)日：2012-05-15

申请号：US12035906

申请日：2008-02-22

申请人： Arthur J. O'Neill, Jr. ,  Michael F. Fee ,  Pak-kin Mak

发明人： Arthur J. O'Neill, Jr. ,  Michael F. Fee ,  Pak-kin Mak

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/123 ,  G06F12/0859

摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.

摘要翻译： 在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。 该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间 当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递 并选择要从缓存目录中抛出的LRU地址。

公开(公告)号：US07934059B2

公开(公告)日：2011-04-26

申请号：US12021781

申请日：2008-01-29

申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

公开(公告)号：US20090193198A1

公开(公告)日：2009-07-30

申请号：US12021781

申请日：2008-01-29

申请人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

发明人： Vesselina K. Papazova ,  Michael A. Blake ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Craig R. Waters

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/507

摘要： A method of preventing lockout and stalling conditions in a multi-node system having a plurality of nodes which includes initiating a processor request to a shared level of cache in a requesting node, performing a fabric coherency establishment sequence on the plurality of nodes, issuing a speculative memory fetch request to a memory, detecting a conflict on one of the plurality of nodes and communicating the conflict back to the requesting node within the system, canceling the speculative memory fetch request issued, and repeating the fabric coherency establishment sequence in the system until the point of conflict is resolved, without issuing another speculative memory fetch request. The subsequent memory fetch request is only issued after determining the state of line within the system, after the successful completion of the multi-node fabric coherency establishment sequence.

摘要翻译： 一种在具有多个节点的多节点系统中防止锁定和停顿状态的方法，包括：向请求节点中的高速缓存的共享级别发起处理器请求，在所述多个节点上执行结构一致性建立序列，发出 对存储器的推测性存储器提取请求，检测多个节点中的一个节点上的冲突并将冲突传送回系统内的请求节点，取消发出的推测性存储器提取请求，并重复系统中的结构一致性建立序列，直到 解决冲突的点，而不发出另一个推测性的内存提取请求。 随后的内存提取请求仅在确定多节点结构一致性建立序列成功完成后确定系统中的线路状态之后发出。

公开(公告)号：US20090216955A1

公开(公告)日：2009-08-27

申请号：US12035906

申请日：2008-02-22

申请人： Arthur J. O'Neill, JR. ,  Michael F. Fee ,  Pak-kin Mak

发明人： Arthur J. O'Neill, JR. ,  Michael F. Fee ,  Pak-kin Mak

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/0859

摘要： A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory.

摘要翻译： 在多处理器系统中用于最近最少使用（LRU）隔室捕获的两个管道通过方法。 该方法包括：通过请求处理器接收提取请求，并基于接收的提取请求访问高速缓存目录;通过确定高速缓存目录中是否发生了提取命中或提取丢失，执行第一管道通路，以及确定LRU隔间 当确定已经发生提取未命中时，基于所接收的获取请求与缓存目录的指定同余类相关联，并且通过使用确定的LRU隔离区和指定的一致等级来访问高速缓存目录来执行第二管道传递 并选择要从缓存目录中抛出的LRU地址。

公开(公告)号：US20060184750A1

公开(公告)日：2006-08-17

申请号：US11402599

申请日：2006-04-12

申请人： Michael Blake ,  Pak-kin Mak ,  Adrian Seigler ,  Gary VanHuben

发明人： Michael Blake ,  Pak-kin Mak ,  Adrian Seigler ,  Gary VanHuben

IPC分类号： G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0831

摘要： A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions with respect to said second ring. A receiver receives a plurality of incoming messages via the first or second ring and merges a plurality of incoming message responses with a local outgoing message response to provide a merged response. Each of the plurality of nodes includes any combination of the following: at least one processor, cache memory, a plurality of I/O adapters, and main memory. The system control element includes a plurality of controllers for maintaining coherency in the system.

摘要翻译： 一种共享存储器对称处理系统，包括多个节点，每个节点具有用于路由节点间通信的系统控制元件。 第一环和第二环互连多个节点，其中所述第一环中的数据相对于所述第二环相反的方向流动。 接收器经由第一或第二环接收多个传入消息，并将多个传入消息响应与本地传出消息响应合并以提供合并响应。 多个节点中的每一个包括以下的任何组合：至少一个处理器，高速缓冲存储器，多个I / O适配器和主存储器。 系统控制元件包括用于维持系统中一致性的多个控制器。