发明申请
US20140003566A1 CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME
有权
时钟数据恢复电路和无线模块,包括它们
- 专利标题: CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME
- 专利标题(中): 时钟数据恢复电路和无线模块,包括它们
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申请号: US13985949申请日: 2011-02-17
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公开(公告)号: US20140003566A1公开(公告)日: 2014-01-02
- 发明人: Eiichi Sano , Yoshihito Amemiya
- 申请人: Eiichi Sano , Yoshihito Amemiya
- 申请人地址: JP Sapporo-shi, Hokkaido
- 专利权人: National University Corporation Hokkaido University
- 当前专利权人: National University Corporation Hokkaido University
- 当前专利权人地址: JP Sapporo-shi, Hokkaido
- 国际申请: PCT/JP2011/053416 WO 20110217
- 主分类号: H04L7/06
- IPC分类号: H04L7/06
摘要:
A clock data recovery circuit includes a ring oscillator, an oscillation control circuit unit to start or stop the ring oscillator according to existence or absence of a PWM signal, a counter circuit unit to count pulse signals to hold N bits of count value, a register circuit unit which is configured to transmit upper M bits of count value, as a reference count value, in response to a transmission signal, a comparison circuit unit to output a timing clock when the count value exceeds the reference count value, and a transmission control circuit unit to be synchronized with a rising timing of the PWM signal to generate the transmission signal and a reset signal for resetting the counter circuit unit.
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