公开(公告)号：US11805026B2

公开(公告)日：2023-10-31

申请号：US16993678

申请日：2020-08-14

申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

发明人： Stanley Ames Lackey, Jr. ,  Damon Tohidi ,  Gerald R. Talbot ,  Edoardo Prete

IPC分类号： H04L41/147 ,  H04L43/50 ,  H04L43/0852 ,  H04L7/10 ,  H04L43/0823 ,  H04L25/14 ,  H04L7/06 ,  H04L7/00 ,  H04L7/04

CPC分类号： H04L41/147 ,  H04L7/06 ,  H04L7/10 ,  H04L25/14 ,  H04L43/0823 ,  H04L43/0852 ,  H04L43/50 ,  H04L7/0041 ,  H04L7/043

摘要： Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

公开(公告)号：US11784785B2

公开(公告)日：2023-10-10

申请号：US17728470

申请日：2022-04-25

申请人： Broadcom International Pte. Ltd.

发明人： Jeffrey Grundvig

IPC分类号： H04L7/04 ,  H04L7/06

CPC分类号： H04L7/06

摘要： Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

公开(公告)号：US20230239132A1

公开(公告)日：2023-07-27

申请号：US18194355

申请日：2023-03-31

申请人： NVIDIA Corporation

发明人： Vishnu Balan ,  Mohammad Mobin ,  Akshay Shyam Pavagada Raghavendra ,  Pervez Mirza Aziz

IPC分类号： H04L7/00 ,  H04L25/03 ,  H04L7/06

CPC分类号： H04L7/0058 ,  H04L7/0079 ,  H04L25/03878 ,  H04L7/0091 ,  H04L25/03006 ,  H04L7/06 ,  H04L2025/03611

摘要： An integrated circuit for a receiving link device includes a processing device to detect, using an equalizer of the receiving link device, that a receiver (RX) pre-cursor value is outside of a threshold value based on a target RX tap value. The processing device further generates, based on the detecting, a plurality of tap messages having a plurality of up or down commands to one of decrease or increase a corresponding transmitter (TX) pre-cursor value of a transmitting link device. The processing device further causes the plurality of tap messages to be provided to a local transmitter to be transmitted to the transmitting link device. The plurality of tap messages is to cause the transmitting link device to adjust the corresponding TX pre-cursor value.

公开(公告)号：US11641268B2

公开(公告)日：2023-05-02

申请号：US17570145

申请日：2022-01-06

申请人： Synopsys, Inc.

发明人： Pramod Bettagere Krishnamurthy

IPC分类号： H04L25/38 ,  H04L7/06 ,  H03M7/40

摘要： Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.

公开(公告)号：US11575405B1

公开(公告)日：2023-02-07

申请号：US17530475

申请日：2021-11-19

申请人： Ufi Space co., Ltd.

发明人： Yu-Min Wang ,  Yu Chih Wang

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04B1/7087 ,  H04L7/06

摘要： The disclosure provides a method for correcting a 1 pulse per second (1PPS) signal and a timing receiver. In the embodiments of the disclosure, the proposed method allows the timing receiver to provide a corrected 1PPS signal with better quality to back-end slave devices, thereby ensuring that the synchronization effect of the slave devices is not overly affected by jitter in a single 1PPS signal.

公开(公告)号：US20220376884A1

公开(公告)日：2022-11-24

申请号：US17833971

申请日：2022-06-07

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Manish BHARDWAJ ,  Venkataratna Subrahmanya Bharathi AKONDY ,  Shamim CHOUDHURY

IPC分类号： H04L7/00 ,  H04L7/06

摘要： A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

公开(公告)号：US20220231830A1

公开(公告)日：2022-07-21

申请号：US17570145

申请日：2022-01-06

申请人： Synopsys, Inc.

发明人： Pramod BETTAGERE KRISHNAMURTHY

IPC分类号： H04L7/06 ,  H03M7/40

摘要： Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.

公开(公告)号：US20220124655A1

公开(公告)日：2022-04-21

申请号：US17418952

申请日：2019-12-23

申请人： ZTE CORPORATION

发明人： Wei LIU ,  Jie CHEN ,  Xianjun LU ,  Xiong PAN ,  Liang YAN

IPC分类号： H04W56/00 ,  H04L7/033 ,  H04L7/06

摘要： The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

公开(公告)号：US20220085956A1

公开(公告)日：2022-03-17

申请号：US17421586

申请日：2020-01-09

申请人： SHARP KABUSHIKI KAISHA ,  FG Innovation Company Limited

发明人： ZHANPING YIN

IPC分类号： H04L5/00 ,  H04L1/18 ,  H04L7/06

摘要： A user equipment (UE) is described. The UE includes a higher layer processor configured to determine a physical uplink control channel (PUCCH) resource in a slot or a subslot for HARQ-ACK feedback for ultra-reliable low-latency communication (URLLC) physical downlink shared channel (PDSCH) transmissions. The PUCCH resource is specified as an enhanced PUCCH format configured to satisfy URLLC PUCCH reliability requirements. The UE also includes transmitting circuitry configured to transmit the HARQ-ACK feedback for the URLLC PDSCH transmissions based on the determined PUCCH resource.

公开(公告)号：US20210176103A1

公开(公告)日：2021-06-10

申请号：US17254696

申请日：2019-06-21

申请人： SAFRAN DATA SYSTEMS ,  CENTRE NATIONAL D'ETUDES SPATIALES

发明人： Alain THOMAS ,  Jean-Marc LEVEAU ,  Stanislas AUGARDE ,  Emmanuel BOUISSON ,  Adrien GAY

IPC分类号： H04L27/233 ,  H04L7/06 ,  H04B1/00

摘要： Method for processing a sequence of digital signal samples comprising a first sub-sequence and a second sub-sequence, said method comprising: forming (106) a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence; demodulating (108) the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols, the second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples (E6-E9), which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence; and reconstructing (114) a sequence of symbols by concatenating the first symbol block with the second symbol block.