发明申请
US20140062521A1 WIRING DEFECT INSPECTING METHOD, WIRING DEFECT INSPECTING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
审中-公开
接线缺陷检查方法，接线缺陷检查装置及制造半导体基板的方法
- 专利标题： WIRING DEFECT INSPECTING METHOD, WIRING DEFECT INSPECTING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
- 专利标题（中）： 接线缺陷检查方法，接线缺陷检查装置及制造半导体基板的方法
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申请号： US14113462申请日： 2012-04-25
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公开(公告)号： US20140062521A1公开(公告)日： 2014-03-06
- 发明人: Eiji Yamada
- 申请人： Eiji Yamada
- 申请人地址： JP Osaka-shi, Osaka
- 专利权人： SHARP KABUSHIKI KAISHA
- 当前专利权人： SHARP KABUSHIKI KAISHA
- 当前专利权人地址： JP Osaka-shi, Osaka
- 优先权： JP2011-097531 20110425
- 国际申请： PCT/JP2012/061117 WO 20120425
- 主分类号： G01R31/26
- IPC分类号： G01R31/26 ; G01R31/02
摘要：
A wiring defect inspecting method in accordance with the present invention comprises: obtaining a resistance of a short-circuited path of a semiconductor substrate; applying a voltage, which is specified on the basis of the resistance obtained, to the semiconductor substrate having a defect portion so as to cause the defect portion to generate heat; and capturing, with use of an infrared camera, an image of the semiconductor substrate whose temperature has increased due to the heat generated from the defect portion.
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